M29W128GL70ZA6E NUMONYX, M29W128GL70ZA6E Datasheet - Page 13

• Manufacturer Part Number: M29W128GL70ZA6E
• Description: IC FLASH 128MBIT 70NS 64TBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W128GL70ZA6E

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16Mx8, 8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Package: 64TBGA
• Cell Type: NOR
• Density: 128 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 128KByte x 128
• Timing Type: Asynchronous
• Interface Type: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2
2.1
2.2
2.3
2.4
2.5
2.6
Signal descriptions
See
connected to this device.
Address inputs (A0-A22)
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the program/erase controller.
Data inputs/outputs (DQ0-DQ7)
The data I/O outputs the data stored at the selected address during a bus read operation.
During bus write operations they represent the commands sent to the command interface of
the internal state machine.
Data inputs/outputs (DQ8-DQ14)
The data I/O outputs the data stored at the selected address during a bus read operation
when BYTE is High, V
impedance. During bus write operations the command register does not use these bits.
When reading the status register these bits should be ignored.
Data inputs/outputs or address inputs (DQ15A 1)
When the device is in x 16 bus mode, this pin behaves as a data input/output pin (as DQ8-
DQ14). When the device operates in x 8 bus mode, this pin behaves as the least significant
bit of the address. Throughout the text consider references to the data input/output to
include this pin when the device operates in x 16 bus mode and references to the address
inputs to include this pin when the device operates in x 8 bus mode except when stated
explicitly otherwise.
Chip enable (E)
The chip enable pin, E, activates the memory, allowing bus read and bus write operations to
be performed. When chip enable is High, V
Output enable (G)
The output enable pin, G, controls the bus read operation of the memory.
Figure 1: Logic
diagram, and
IH
. When BYTE is Low, V
Table 2: Signal
IH
, all other pins are ignored.
IL
, these pins are not used and are high
names, for a brief overview of the signals
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