PC48F4400P0TB0EH NUMONYX, PC48F4400P0TB0EH Datasheet - Page 34

• Manufacturer Part Number: PC48F4400P0TB0EH
• Description: IC FLASH 256MBIT 64EZBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of PC48F4400P0TB0EH

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512M (32Mx16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-EZBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.0.1
11.1
Table 11: Read Configuration Register Description (Sheet 1 of 2)
Datasheet
34
Read Configuration Register (RCR)
15
14:11
10
9
8
7
6
5:4
Mode
Read
RM
Bit
15
Read Mode (RM)
Latency Count (LC[3:0])
WAIT Polarity (WP)
Reserved (R)
WAIT Delay (WD)
Burst Sequence (BS)
Clock Edge (CE)
Reserved (R)
14
Latency Count
Clear Status Register
The Clear Status Register command clears the status register. It functions independent
of VPP. The WSM sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing
them. The Status Register should be cleared before starting a command sequence to
avoid any ambiguity. A device reset also clears the Status Register.
Read Configuration Register
The RCR is used to select the read mode (synchronous or asynchronous), and it defines
the synchronous burst characteristics of the device. To modify RCR settings, use the
Configure Read Configuration Register command (see
Bus Cycles” on page
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (see
The RCR is shown in
13
LC[3:0]
Name
12
11
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
0010 =Code 2
0011 =Code 3
0100 =Code 4
0101 =Code 5
0110 =Code 6
0111 =Code 7
1000 =Code 8
1001 =Code 9
1010 =Code 10
1011 =Code 11
1100 =Code 12
1101 =Code 13
1110 =Code 14
1111 =Code 15 (default)
(Other bit settings are reserved)
0 =WAIT signal is active low (default)
1 =WAIT signal is active high
Default “0”, Non-changeable
0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
Default “0”, Non-changeable
0 = Falling edge
1 = Rising edge (default)
Default “0”, Non-changeable
Polarity
WAIT
WP
10
18).
Table
RES
11. The following sections describe each RCR bit.
R
9
Section 7.3, “Read Device Identifier” on page
WAIT
Delay
WD
8
Burst
Seq
BS
7
Edge
CLK
CE
6
Description
RES
R
5
Section 6.2, “Device Command
RES
R
4
Burst
Wrap
BW
3
Order Number: 320003-09
2
Burst Length
BL[2:0]
22).
1
P33-65nm
Mar 2010
0