CAT24C04YI-G ON Semiconductor, CAT24C04YI-G Datasheet - Page 4

• Manufacturer Part Number: CAT24C04YI-G
• Description: IC EEPROM SERIAL 4KB I2C 8TSSOP
• Manufacturer: ON Semiconductor

Specifications of CAT24C04YI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Organization: 512 x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.7 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.8 V , 2.5 V , 3.3 V , 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
after V
down into Reset mode when V
trigger level. This bi−directional POR feature protects the
device against ‘brown−out’ failure following a temporary
loss of power.
*For common features, the CAT24C01/02/04/08/16 will be
referred to as CAT24Cxx.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Functional Description
(I
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24Cxx acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.
I
two wires are connected to the V
resistors. Master and Slave devices connect to the 2−wire
2
Table 6. A.C. TEST CONDITIONS
C Bus Protocol
2
Input Drive Levels
Input Rise and Fall Time
Input Reference Levels
Output Reference Level
Output Test Load
Each CAT24Cxx* incorporates Power−On Reset (POR)
A CAT24Cxx device will power up into Standby mode
The CAT24Cxx supports the Inter−Integrated Circuit
The I
C) Bus data transmission protocol, which defines a device
CC
2
C bus consists of two ‘wires’, SCL and SDA. The
exceeds the POR trigger level and will power
CC
CC
drops below the POR
0.2 x V
v 50 ns
0.3 x V
0.5 x V
Current Source I
supply via pull−up
CC
CC
CC
, 0.7 x V
to 0.8 x V
http://onsemi.com
OL
CC
= 3 mA (V
CC
4
CC
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
busy (see AC Characteristics).
while the SCL line is high. An SDA transition while SCL is
high will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
Device Addressing
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
Figure 3. A
address pins, and a
Acknowledge
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
Data transfer may be initiated only when the bus is not
During data transfer, the SDA line must remain stable
The Master initiates data transfer by creating a START
After processing the Slave address, the Slave responds
w 2.5 V); I
2
OL
, A
= 1 mA (V
1
and A
10
, a
0
9
CC
must match the state of the external
and a
< 2.5 V); C
8
are internal address bits.
L
= 100 pF
th
clock cycle. As