CAT93C46RYI-G ON Semiconductor, CAT93C46RYI-G Datasheet - Page 6

• Manufacturer Part Number: CAT93C46RYI-G
• Description: IC EEPROM 1KBIT 4MHZ 8TSSOP
• Manufacturer: ON Semiconductor

Specifications of CAT93C46RYI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 1K (128 x 8 or 64 x 16)
• Speed: 4MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 93C46RYI-G

Write
the CS (Chip Select) pin must be deselected for a minimum
of t
CS will start the self clocking clear and data store cycle of
the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device and
polling the DO pin. Since this device features Auto−Clear
before write, it is NOT necessary to erase a memory location
before it is written into.
Erase
(Chip Select) pin must be deasserted for a minimum of
t
Note). The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
Erase All
pin must be deselected for a minimum of t
CSMIN
DO
SK
CS
SK
CS
DI
After receiving a WRITE command, address and the data,
Upon receiving an ERASE command and address, the CS
Upon receiving an ERAL command, the CS (Chip Select)
DI
CSMIN
after the proper number of clock pulses (See Design
(See Design Note for details). The falling edge of
1
1
0
0
1
0
* ENABLE = 11
DISABLE = 00
A
N
Figure 5. EWEN/EWDS Instruction Timing
A
*
N−1
CSMIN
Figure 6. Write Instruction Timing
HIGH−Z
. The falling
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A
0
6
D
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C46R can be
determined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to a
logical “1” state.
Write All
(Chip Select) pin must be deselected for a minimum of
t
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
Design Note
sampled, Chip Select (CS) must be brought Low before the
next rising edge of the clock (SK) in order to start the
self−timed high voltage cycle. This is important because if
the CS is brought low before or after this specific frame
window, the addressed location will not be programmed or
erased.
N
CSMIN
Upon receiving a WRAL command and data, the CS
With CAT93C46R, after the last data bit has been
. The falling edge of CS will start the self clocking
D
0
t
SV
t
EW
t
CS MIN
STATUS
VERIFY
BUSY
STANDBY
READY
HIGH−Z
STANDBY
t
HZ