SST25VF040B-50-4I-QAF Microchip Technology, SST25VF040B-50-4I-QAF Datasheet - Page 17

• Manufacturer Part Number: SST25VF040B-50-4I-QAF
• Description: IC FLASH SER 4MB 50MHZ SPI 8WSON
• Manufacturer: Microchip Technology

Specifications of SST25VF040B-50-4I-QAF

• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-WSON
• Format - Memory: FLASH
• Speed: 50MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Architecture: Sectored
• Interface Type: SPI
• Access Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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©2011 Silicon Storage Technology, Inc.
Chip-Erase
Read-Status-Register (RDSR)
The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored
if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence.
The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven
high before the instruction is executed. The user may poll the Busy bit in the software status register or wait
T
sequence.
Figure 15:Chip-Erase Sequence
The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register
may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in
progress, the Busy bit may be checked before sending any new commands to assure that the new
commands are properly received by the device. CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing
clock cycles until it is terminated by a low to high transition of the CE#. See Figure 16 for the RDSR
instruction sequence.
Figure 16:Read-Status-Register (RDSR) Sequence
CE
for the completion of the internal self-timed Chip-Erase cycle. See Figure 15 for the Chip-Erase
SCK
CE#
SO
SI
MODE 3
MODE 0
MSB
0
1
HIGH IMPEDANCE
2
SCK
CE#
SO
3
SI
05
MODE 3
MODE 0
4
17
5
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
6
60 or C7
7
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
8
4 Mbit SPI Serial Flash
1295 ChEr.0
9
10
Register Out
11
Status
12
SST25VF040B
13
14
1295 RDSRseq.0
S71295-06-000
Data Sheet
02/11