AT25640-10PI Atmel, AT25640-10PI Datasheet - Page 6

• Manufacturer Part Number: AT25640-10PI
• Description: IC EEPROM 64KBIT 3MHZ 8DIP
• Manufacturer: Atmel

Specifications of AT25640-10PI

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 3MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Interface
Description
6
AT25080/160/320/640
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080/160/320/640
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25080/160/320/640 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25080/160/320/640, and the serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25080/160/320/640 is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO)
will remain in a high impedance state.
H O L D : T h e H O L D p i n i s u s e d i n c o n j u n c t i o n w i t h t h e C S p i n t o s e l e c t t h e
AT25080/160/320/640. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without resetting
the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low.
To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK
may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the
high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when
held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the sta-
tus register are inhibited. WP going low while CS is still low will interrupt a write to the status
register. If the internal write cycle has already been initiated, WP going low will have no effect
on any write operation to the status register. The WP pin function is blocked when the WPEN
bit in the status register is “0”. This will allow the user to install the AT25080/160/320/640 in a
system with the WP pin tied to ground and still be able to write to the status register. All WP
pin functions are enabled when the WPEN bit is set to “1”.
0675M–SEEPR–9/03