AT45DB321B-CI Atmel, AT45DB321B-CI Datasheet
AT45DB321B-CI
Specifications of AT45DB321B-CI
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AT45DB321B-CI Summary of contents
Page 1
... Commercial and Industrial Temperature Ranges Description The AT45DB321B is a 2.7-volt only, serial interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each itio AT4 lso ain s two SR AM data buffers of 528 bytes each ...
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... FFH. Block Diagram Memory Array To provide optimal flexibility, the memory array of the AT45DB321B is divided into three levels of granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis ...
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... Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock AT45DB321B PAGE ARCHITECTURE 8 Pages PAGE 0 ...
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... STATUS REGISTER READ: The status register can be used to determine the device’s Ready/Busy status, the result of a Main Memory Page to Buffer Compare operation, or the device density. To read the status register, an opcode of 57H or D7H must be AT45DB321B 4 specification. The Continuous Array Read bypasses both data buff- CAR 2223E– ...
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... The device density is indicated using bits and 2 of the status register. For the AT45DB321B, the four bits are and 1. The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of Serial DataFlash devices, allowing a total of sixteen dif- ferent density configurations ...
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... AT45DB321B 6 . During this time, the status register will indicate that the part is busy During this time, the status register will indicate that the part is busy. BE PA8 PA7 PA6 PA5 • ...
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... The operation is internally self-timed and should take place in a maximum time of t register will indicate that the part is busy. AT45DB321B . During EP ), the status XFR ...
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... CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the device is not selected, data will not be accepted on the SI pin, and the SO pin will remain in a high-impedance state. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition on the CS pin is required to end an operation. AT45DB321B 8 2223E–DFLASH–11//03 ...
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... When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI Mode 3. In addition, the SO pin will high-impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruc- tion. The SPI mode will be automatically selected on every falling edge sampling the inactive clock state. AT45DB321B 9 ...
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... Auto Page Rewrite through Buffer 2 Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3). AT45DB321B 10 SCK Mode Inactive Clock Polarity Low or High ...
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... P P 89H D2H D4H D6H D7H E8H Note Reserved Bit P = Page Address Bit B = Byte/Buffer Address Bit x = Don’t Care 2223E–DFLASH–11//03 Address Byte Address Byte N/A N N/A N AT45DB321B Address Byte N N Additional Don’t Care Bytes Required Bytes x x ...
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... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT45DB321B - 2.7V to 3.6V Min Typ Max ...
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... XFR t Page Erase and Programming Time EP t Page Programming Time P t Page Erase Time PE t Block Erase Time BE t RESET Pulse Width RST t RESET Recovery Time REC 2223E–DFLASH–11//03 AT45DB321B AT45DB321B Min Max Units 20 MHz 20 MHz 250 ns 250 ns 250 ns 200 ns 5 ...
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... SPI Mode 3. Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0 CS SCK HIGH IMPEDANCE SO SI Waveform 2 – Inactive Clock Polarity High and SPI Mode CSS SCK HIGH AT45DB321B 14 2.4V AC 2.0 DRIVING 0.8 LEVELS 0.45V , t < (10 DEVICE UNDER ...
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... For densities larger than 32M bits, the “r” bits become the most significant Page Address bit for the appropriate density. 2223E–DFLASH–11//03 SI CMD 8 bits 8 bits Page Address Byte/Buffer Address (PA12-PA0) (BA9-BA0/BFA9-BFA0) AT45DB321B t t REC CSS t RST HIGH IMPEDANCE 8 bits LSB 15 ...
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... Buffer Write CS SI CMD Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles AT45DB321B 16 FLASH MEMORY ARRAY MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 2 MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 1 I/O INTERFACE ...
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... FLASH MEMORY ARRAY MAIN MEMORY PAGE READ I/O INTERFACE SO PA5-0, BA9-8 BA7-0 X Starts reading page data into buffer CMD r , PA12-6 PA5-0, XX CMD X X···X, BFA9-8 BFA7-0 AT45DB321B MAIN MEMORY PAGE TO BUFFER 2 BUFFER 2 (528 BYTES) BUFFER 2 READ n 1st byte read ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity Low Continuous Array Read (Opcode: 68H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: 52H) CS SCK COMMAND OPCODE AT45DB321B DATA OUT HIGH-IMPEDANCE LSB MSB BIT 4223 BIT PAGE n PAGE n DATA OUT MSB 2223E–DFLASH–11//03 ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued) Buffer Read (Opcode: 54H or 56H) CS SCK COMMAND OPCODE Status Register Read (Opcode: 57H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO 2223E–DFLASH–11// HIGH-IMPEDANCE AT45DB321B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB MSB 19 ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity High Continuous Array Read (Opcode: 68H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: 52H) CS SCK COMMAND OPCODE AT45DB321B DATA OUT HIGH-IMPEDANCE LSB MSB BIT 4223 BIT PAGE n PAGE n DATA OUT MSB 2223E–DFLASH–11//03 ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued) Buffer Read (Opcode: 54H or 56H) CS SCK COMMAND OPCODE Status Register Read (Opcode: 57H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO 2223E–DFLASH–11// HIGH-IMPEDANCE AT45DB321B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB MSB 21 ...
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... Detailed Bit-level Read Timing – SPI Mode 0 Continuous Array Read (Opcode: E8H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45DB321B DATA OUT HIGH-IMPEDANCE LSB MSB BIT 4223 BIT PAGE n PAGE n DATA OUT MSB 2223E–DFLASH–11// ...
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... Detailed Bit-level Read Timing – SPI Mode 0 (Continued) Buffer Read (Opcode: D4H or D6H) CS SCK COMMAND OPCODE Status Register Read (Opcode: D7H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO 2223E–DFLASH–11// HIGH-IMPEDANCE AT45DB321B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB MSB 23 ...
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... Detailed Bit-level Read Timing – SPI Mode 3 Continuous Array Read (Opcode: E8H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45DB321B DATA OUT HIGH-IMPEDANCE LSB MSB BIT 4223 BIT PAGE n PAGE n DATA OUT MSB 2223E–DFLASH–11// ...
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... Detailed Bit-level Read Timing – SPI Mode 3 (Continued) Buffer Read (Opcode: D4H or D6H) CS SCK COMMAND OPCODE Status Register Read (Opcode: D7H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO 2223E–DFLASH–11// HIGH-IMPEDANCE AT45DB321B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB MSB 25 ...
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... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB321B 26 START provide address ...
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... END PA9 PA8 PA7 • • • • • • • • • AT45DB321B If planning to modify multiple bytes currently stored within a page of the Flash array PA6 PA5 PA4 PA3 • • • • • • • • • • • • X ...
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... Array), 1.0 mm Pitch, Plastic Chip-scale Ball Grid Array (CBGA) 28R 28-lead, 0.330" Wide, Plastic Gull Wing Small Outline Package (SOIC) 32T 32-lead, Plastic Thin Small Outline Package (TSOP) AT45DB321B 28 Ordering Code AT45DB321B-CC AT45DB321B-RC AT45DB321B-TC AT45DB321B-CI AT45DB321B-RI AT45DB321B-TI Package Type Package Operation Range 44C1 Commercial 28R ( 32T ...
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... San Jose, CA 95131 R 2223E–DFLASH–11// BALL CORNER 2.00 REF D1 b TITLE 44C1, 44-ball ( Array 1.2 mm Body, 1.0 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) AT45DB321B SIDE VIEW A1 A COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL E 5.90 6.00 6.10 E1 – ...
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... This package conforms to JEDEC reference MO-142, Variation BD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. TITLE 2325 Orchard Parkway San Jose, CA 95131 R AT45DB321B 30 PIN 1 0º ~ 8º SEATING PLANE ...
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... Mold Flash or protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 2223E–DFLASH–11// TITLE 28R, 28-lead, 0.330" Body Width, Plastic Gull Wing Small Outline (SOIC) AT45DB321B COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM NOTE A 2.39 – 2.79 A1 0.002 – ...
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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...