AT49F512-70JC Atmel, AT49F512-70JC Datasheet
AT49F512-70JC
Specifications of AT49F512-70JC
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AT49F512-70JC Summary of contents
Page 1
... Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F512 is performed by erasing the entire 512K of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 10 µs. The end of a program cycle can be optionally detected by the DATA polling feature ...
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... Pin Configurations Pin Name A0 - A15 I/O0 - I/O7 NC 2.1 32PLCC Top View 2.2 32VSOP/32TSOP (Type 1)Top View AT49F512 2 Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect I/ A11 A13 4 A14 VCC A15 11 A12 A14 A13 A8 A9 A11 OE A10 CE I/ A10 ...
Page 3
... Device Operation 4.1 Read The AT49F512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever high. This dual-line control gives designers flexibility in preventing bus contention ...
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... DATA Polling The AT49F512 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin ...
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... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT49F512 6th Bus Cycle Addr Data 5555 10 ...
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... A1 - A15 = A15 = A15 = V IH Condition MHz OUT -400 µ -100 µ 4. AT49F512-70 -40°C - 85°C 5V ± 10% 5V ± 10 OUT High Z High Z ( Manufacturer Code Device Code H IH Manufacturer Code IL Device Code IL Min Max 10 10 300 3 40 0.8 2.0 0.45 2 ...
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... whichever occurs first ( This parameter is characterized and is not 100% tested. 1027H–FLASH–10/05 AT49F512-55 Min 0 0 (1)(2)(3)( after the address transition without impact on t ACC after the falling edge of CE without impact pF). L AT49F512 AT49F512-70 Max Min Max ACC after an address change CE ...
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... Input Test Waveforms and Measurement Level < 13. Output Test Load 14. Pin Capacitance ( MHz, T= 25°C Symbol Typ OUT Note: 1. This parameter is characterized and is not 100% tested. AT49F512 8 Max Units Conditions OUT 1027H–FLASH–10/05 ...
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... Chip Select Set-up Time CS t Chip Select Hold Time CH t Write Pulse Width ( Data Set-up Time Data, OE Hold Time DH OEH t Write Pulse Width High WPH 16. AC Byte Load Waveforms 16.1 WE Controlled 16.2 CE Controlled 1027H–FLASH–10/05 AT49F512 Min Max Units ...
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... Write Pulse Width High WPH t Erase Cycle Time EC 18. Program Cycle Waveforms A0-A15 DATA 19. Chip Erase Cycle Waveforms A0-A15 5555 DATA BYTE 0 Note must be high only when WE and CE are both low. AT49F512 10 PROGRAM CYCLE WPH 5555 5555 2AAA WPH 2AAA 5555 ...
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... Toggling either both OE and CE will operate toggle bit. The t input(s) 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 1027H–FLASH–10/05 (1) t OEH t HIGH (1) (1)(2)(3) AT49F512 Min Typ Max Min Typ Max 10 10 ...
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... LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 40 TO ADDRESS 5555 (2) PAUSE 1 second 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled. AT49F512 12 ...
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... Note: 1. The AT49F512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block the higher address range should contact Atmel. ...
Page 14
... Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010 (0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004 (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT49F512 14 1.14(0.045 PIN NO. 1 IDENTIFIER ...
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... MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 E 7.90 8.00 8.10 L 0.50 0.60 0.70 L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.50 BASIC DRAWING NO. AT49F512 NOTE Note 2 Note 2 10/18/01 REV. 32T B 15 ...
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... E Notes: 1. This package conforms to JEDEC reference MO-142, Variation BA. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT49F512 16 PIN SEATING PLANE A1 TITLE ...
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... Converted datasheet to New Template. • Added Green Package (Pb/Halide-free) Option in the Ordering Information section. • Added 55 ns TSOP Green Option • Removed 70 ns Green Option • Removed 55JI Option • Added 70 ns TSOP Green Option AT49F512 17 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...