AT24C08A-10PI-2.5 Atmel, AT24C08A-10PI-2.5 Datasheet - Page 4

IC EEPROM 8KBIT 400KHZ 8DIP

AT24C08A-10PI-2.5

Manufacturer Part Number
AT24C08A-10PI-2.5
Description
IC EEPROM 8KBIT 400KHZ 8DIP
Manufacturer
Atmel
Datasheet

Specifications of AT24C08A-10PI-2.5

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
8K (1K x 8)
Speed
100kHz, 400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT24C08A10PI2.5
AC Characteristics
Applicable over recommended operating range from T
100 pF (unless otherwise noted).
Note:
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
4
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Endurance
SCL
LOW
HIGH
I
AA
BUF
HD.STA
SU.STA
HD.DAT
SU.DAT
R
F
SU.STO
DH
WR
1. This parameter is characterized and is not 100% tested.
(1)
AT24C02A/04A/08A
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free before
a new transmission can start
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
Inputs Fall Time
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25 C, Page Mode
(1)
(1)
(1)
(1)
A
= -40 C to +85 C, V
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8 bit words
The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock
cycle.
STANDBY MODE: The AT24C02A/04A/08A features a low
power standby mode which is enabled: (a) upon power-up
and (b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:(a) Clock up to 9 cycles, (b) look for SDA
high in each cycle while SCL is high and then (c) create a
start condition as SDA is high.
2.7-, 2.5-, 1.8-volt
CC
Min
200
100
4.7
4.0
0.1
4.7
4.0
4.7
4.7
1M
0
= +1.8V to +5.5V, CL = 1 TTL Gate and
Max
100
100
300
4.5
1.0
10
Min
100
1.2
0.6
0.1
1.2
0.6
0.6
0.6
1M
50
0
5.0-volt
Max
300
400
0.9
0.3
50
10
Cycles
Units
Write
kHz
ms
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
.

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