AT29C256-70PI Atmel, AT29C256-70PI Datasheet - Page 3

• Manufacturer Part Number: AT29C256-70PI
• Description: IC FLASH 256KBIT 70NS 28DIP
• Manufacturer: Atmel

Specifications of AT29C256-70PI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256K (32K x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT29C25670PI

3. Block Diagram
4. Device Operation
4.1
4.2
4.3
0046S–FLASH–2/07
Read
Byte Load
Program
The AT29C256 is accessed like a static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state whenever CE or OE is high. This dual-line con-
trol gives designers flexibility in preventing bus contention.
A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low
(respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever
occurs last. The data is latched by the first rising edge of CE or WE. Byte loads are used to enter
the 64 bytes of a page to be programmed or the software codes for data protection and chip
erasure.
The device is reprogrammed on a page basis. If a byte of data within a page is to be changed,
data for the entire page must be loaded into the device. Any byte that is not loaded during the
programming of its page will be indeterminate. Once the bytes of a page are loaded into the
device, they are simultaneously programmed during the internal programming period. After the
first data byte has been loaded into the device, successive bytes are entered in the same man-
ner. Each new byte to be programmed must have its high-to-low transition on WE (or CE) within
150 µs of the low-to-high transition of WE (or CE) of the preceding byte. If a high-to-low transi-
tion is not detected within 150 µs of the last low-to-high transition, the load period will end and
the internal programming period will start. A6 to A14 specify the page address. The page
address must be valid during each high-to-low transition of WE (or CE). A0 to A5 specify the
byte address within the page. The bytes may be loaded in any order; sequential loading is not
required. Once a programming operation has been initiated, and for the duration of t
operation will effectively be a polling operation.
AT29C256
WC
, a read
3