AT25080A-10TI-1.8 Atmel, AT25080A-10TI-1.8 Datasheet
AT25080A-10TI-1.8
Specifications of AT25080A-10TI-1.8
Related parts for AT25080A-10TI-1.8
AT25080A-10TI-1.8 Summary of contents
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... PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8- lead TSSOP and 8-Lead Ultra Leadframe Land Grid Array (ULLGA) packages. The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK) ...
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... Absolute Maximum Ratings* Operating Temperature ................................ –55C to +125C Storage Temperature.................................... –65C to +150C Voltage on Any Pin with Respect to Ground ....................................–1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA AT25080A/160A/320A/640A 2 8-lead SOIC 8-lead PDIP VCC ...
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... Applicable over recommended operating range from T Symbol Test Conditions C Output Capacitance (SO) OUT C Input Capacitance (CS, SCK, SI, WP, HOLD) IN Note: 1. This parameter is characterized and is not 100% tested. 3347L–SEEPR–06/07 AT25080A/160A/320A/640A Block Diagram = 25 1.0 MHz +5.0V (unless otherwise noted) CC Max Units Conditions ...
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... Output High-voltage OH1 V Output Low-voltage OL2 V Output High-voltage OH2 Notes min and V max are reference only and are not tested Worst case measured at 85C AT25080A/160A/320A/640A 4 = 40C to +85C, V – AI Test Condition MHz Open, Read 5. MHz Open, Read, CC Write ...
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... SU t Data In Hold Time H t HOLD Setup Time HD t HOLD Hold Time CD t Output Valid V t Output Hold Time HO 3347L–SEEPR–06/07 AT25080A/160A/320A/640A = 40C to +85 Specified, – Voltage Min 4.5–5.5 0 2.7–5.5 0 1.8–5.5 0 4.5–5.5 2.7–5.5 1.8–5.5 4.5– ...
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... HOLD to Output Low HOLD to Output High Output Disable Time DIS t Write Cycle Time WC (1) Endurance 5.0V, 25°C, Page Mode Note: 1. This parameter is characterized and is not 100% tested. AT25080A/160A/320A/640A 6 = 40C to +85 Specified, – Voltage Min 4.5–5.5 0 2.7–5.5 0 1.8–5.5 0 4.5– ...
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... The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25080A/160A/320A/640A in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “ ...
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... Figure 2-1. AT25080A/160A/320A/640A 8 SPI Serial Interface AT25080A/160A/320A/640A 3347L–SEEPR–06/07 ...
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... The AT25080A/160A/320A/640A is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25080A/160A/320A/640A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in ferred with the MSB first and start with a high-to-low CS transition. ...
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... Bits 0–7 are “1”s during an internal write cycle. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25080A/160A/320A/640A is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read only ...
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... If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle. The AT25080A/160A/320A/640A is capable of a 32-byte page write operation. After each byte of data is received, the five low-order address bits are internally incremented by one; the high- order bits of the address will remain constant ...
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... Table 3-6. Address Don’t Care Bits 4. Timing Diagrams Figure 4-1. Synchronous Data Timing (for Mode CSS V IH SCK HI Figure 4-2. WREN Timing AT25080A/160A/320A/640A 12 Address Key AT25080A AT25160A A A – – VALID IN AT25320A A –A A – –A A – CSH AT25640A A – –A ...
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... Figure 4-3. WRDI Timing Figure 4-4. RDSR Timing SCK INSTRUCTION SI HIGH IMPEDANCE SO Figure 4-5. WRSR Timing SCK INSTRUCTION SI HIGH IMPEDANCE SO 3347L–SEEPR–06/ MSB AT25080A/160A/320A/640A DATA OUT DATA ...
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... Figure 4-6. READ Timing SCK SI INSTRUCTION HIGH IMPEDANCE SO Figure 4-7. WRITE Timing SCK INSTRUCTION SI HIGH IMPEDANCE SO Figure 4-8. HOLD Timing CS SCK HOLD SO AT25080A/160A/320A/640A BYTE ADDRESS ... BYTE ADDRESS ... DATA OUT MSB DATA 3347L–SEEPR–06/07 ...
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... AT25080A Ordering Information Ordering Code (2) AT25080A-10PU-2.7 (2) AT25080A-10PU-1.8 (2) AT25080AN-10SU-2.7 (2) AT25080AN-10SU-1.8 (2) AT25080A-10TU-2.7 (2) AT25080A-10TU-1.8 (2) (Not recommended for new design) AT25080AY1-10YU-1.8 (3) AT25080AY6-10YH-1.8 (4) AT25080A-W1.8-11 Notes: 1. For 2.7V devices used in the 4.5 to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. 2. “U” designates Green package + RoHS compliant. ...
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... Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 8Y6 2x3mm) 8D3 8-lead, 1. 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULLGA) D3 2.7 Low Voltage (2.7 to 5.5V) 1.8 Low Voltage (1.8 to 5.5V) AT25080A/160A/320A/640A 16 (1) Package 8P3 8P3 8S1 8S1 8A2 ...
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... Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8-lead, 2. 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 8Y6 2x3mm) 2.7 Low Voltage (2.7 to 5.5V) 1.8 Low Voltage (1.8 to 5.5V) 3347L–SEEPR–06/07 AT25080A/160A/320A/640A (1) Package 8P3 8P3 8S1 8S1 8A2 8A2 ...
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... Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2. 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 2.7 Low Voltage (2.7 to 5.5V) 1.8 Low Voltage (1.8 to 5.5V) AT25080A/160A/320A/640A 18 (1) Package 8P3 8P3 8S1 ...
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... E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 2325 Orchard Parkway San Jose, CA 95131 R 3347L–SEEPR–06/07 AT25080A/160A/320A/640A ...
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... JEDEC SOIC Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT25080A/160A/320A/640A TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing ...
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... Dimension D and determined at Datum Plane H. 2325 Orchard Parkway San Jose, CA 95131 R 3347L–SEEPR–06/ TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) AT25080A/160A/320A/640A L1 L End View COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM D 2.90 3.00 3 ...
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... MAP D E Top View Side View 2325 Orchard Parkway San Jose, CA 95131 R AT25080A/160A/320A/640A End View A SYMBOL TITLE 8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package (MAP PIN 1 INDEX AREA Bottom View COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE – ...
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... Orchard Parkway San Jose, CA 95131 R 3347L–SEEPR–06/07 Pin 1 Index Area A2 A3 TITLE 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, Dual No Lead Package (DFN) ,(MLP 2x3) AT25080A/160A/320A/640A (6X) A1 1.50 REF. COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM MAX D 2 ...
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... ULLGA PIN # TOP VIEW 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT25080A/160A/320A/640A SIDE VIEW SYMBOL TITLE 8D3, 8-lead (1.80 x 2.20 mm Body) Ultra Leadframe Land Grid Array (ULLGA PIN # BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE – – ...
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... Revision History Doc. Rev. 3347M 3347L 3347K 3347L–SEEPR–06/07 AT25080A/160A/320A/640A Date Comments Added 8D3-ULLGA to document 6/2007 Changed Feature descriptions on page 1 Added AT25640AY6-10YU-1.8 ordering code. 4/2007 Added ‘Not recommended for new design’ note to AT25640AY1- 10YU-1.8 ordering code. Implemented revision history. ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...