AT45DB011B-XU Atmel, AT45DB011B-XU Datasheet

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... Its 1,081,344 bits of memory are organized as 512 pages of 264 bytes each. In addi- tion to the main memory, the AT45DB011B also contains one SRAM data buffer of 264 bytes. The buffer allows receiving of data while a page in the main memory is being reprogrammed ...

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... Block Diagram RDY/BUSY Memory Array To provide optimal flexibility, the memory array of the AT45DB011B is divided into three levels of granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages per sector and block. ...

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... BLOCK ARCHITECTURE SECTOR 0 BLOCK 0 BLOCK 1 BLOCK 2 BLOCK 3 BLOCK 29 BLOCK 30 BLOCK 31 BLOCK 32 BLOCK 33 BLOCK 34 BLOCK 61 BLOCK 62 BLOCK 63 Block = 2112 bytes (2K + 64) AT45DB011B PAGE ARCHITECTURE PAGE 0 8 Pages PAGE 1 PAGE 6 PAGE 7 PAGE 8 PAGE 9 PAGE 14 PAGE 15 PAGE 16 PAGE 17 PAGE 18 PAGE 509 PAGE 510 PAGE 511 ...

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... In the AT45DB011B, the first six address bits are reserved for larger density devices (see Notes on page 15), the next nine address bits (PA8-PA0) specify the page address, and the next nine address bits (BA8-BA0) specify the starting byte address within the page. The 32 don’ ...

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... The device density is indicated using bits and 2 of the status register. For the AT45DB011B, the four bits are and 1. The decimal value of these four binary bits does not equate to the device density; the three bits represent a combinational code relating to dif- fering densities of Serial DataFlash devices, allowing a total of sixteen different density configurations ...

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... Block Erase Addressing PA8 • • • AT45DB011B 6 . During this time, the status register will indicate that the part During this time, the status register will indicate that the BE PA7 PA6 PA5 PA4 ...

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... Figure 2 on page 27 is recommended. Each page within a sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program opera- tions in that sector. 1984J–DFLASH–06/06 . During this time, the status register will indicate that the part is busy. EP AT45DB011B ), the status register can be read to determine XFR ), the status XFR . ...

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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT45DB011B 0°C to 70°C -40°C to 85°C 2.7V to 3.6V 1984J–DFLASH–06/06 ...

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... The only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned. If this pin and feature are not utilized it is recommended that the WP pin be driven high externally. 1984J–DFLASH–06/06 AT45DB011B 9 ...

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... An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. AT45DB011B the minimum datasheet value, the system should wait CC 1984J– ...

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... Inactive Clock Polarity Low or High SPI Mode Inactive Clock Polarity Low or High SPI Mode SCK Mode Any Any Any Any Any Any SCK Mode Any Any Any AT45DB011B Opcode 68H E8H 52H D2H 54H D4H 57H D7H Opcode 84H 83H 88H 81H ...

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... Table 4. Detailed Bit-level Addressing Sequence Opcode Opcode 50H 52H 53H 54H 57H 58H 60H 68H 81H 82H 83H 84H 88H D2H D4H D7H E8H Note Reserved Bit P = Page Address Bit B = Byte/Buffer Address Bit x = Don’t Care AT45DB011B 12 Address Byte Address Byte N/A N ...

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... RESET Pulse Width RST t RESET Recovery Time REC 1984J–DFLASH–06/06 Condition CS, RESET all inputs at IH CMOS levels MHz mA 3.6V OUT 3. CMOS levels CMOS levels I 1 -100 µA OH AT45DB011B Min Typ Max 0.6 2.0 0 0.2V CC Min Typ Max 250 250 250 200 ...

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... SPI Mode 3. Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0 CS SCK HIGH IMPEDANCE SO SI Waveform 2 – Inactive Clock Polarity High and SPI Mode CSS SCK HIGH AT45DB011B 14 2. 2.0 DRIVING MEASUREMENT 0.8 LEVELS LEVEL 0.45V < (10% to 90%) ...

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... It is recommended that “r” logical “0”. 3. For densities larger than 1M bit, the “r” bits become the most significant Page Address bit for the appropriate density. 1984J–DFLASH–06/06 CMD 8 bits 8 bits Page Address Byte/Buffer Address (PA8-PA0) (BA8-BA0/BFA8-BFA0) AT45DB011B t REC t CSS t RST HIGH IMPEDANCE 8 bits LSB 15 ...

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... CMD Buffer Write CS SI CMD Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles AT45DB011B 16 FLASH MEMORY ARRAY PAGE (264 BYTES) BUFFER TO MAIN MEMORY PAGE PROGRAM BUFFER (264 BYTES) BUFFER WRITE ...

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... BUFFER (264 BYTES) BUFFER READ I/O INTERFACE PA6-0, BA8 BA7-0 X Starts reading page data into buffer CMD r ···r , PA8-7 PA6-0, X CMD X X···X, BFA8 BFA7-0 AT45DB011B MAIN MEMORY PAGE READ n 1st byte read n+1 = 2nd byte read n+1 ...

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... Detailed Bit-level Read Timing – Inactive Clock Polarity Low Continuous Array Read (Opcode: 68H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: 52H) CS SCK COMMAND OPCODE AT45DB011B DATA OUT HIGH-IMPEDANCE LSB MSB BIT 2111 BIT PAGE n PAGE n DATA OUT MSB D 5 1984J–DFLASH–06/06 ...

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... Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued) Buffer Read (Opcode: 54H) CS SCK COMMAND OPCODE Status Register Read (Opcode: 57H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO 1984J–DFLASH–06/ HIGH-IMPEDANCE AT45DB011B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB MSB 19 ...

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... Detailed Bit-level Read Timing – Inactive Clock Polarity High Continuous Array Read (Opcode: 68H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: 52H) CS SCK COMMAND OPCODE AT45DB011B DATA OUT HIGH-IMPEDANCE LSB MSB BIT 2111 BIT PAGE n PAGE n DATA OUT MSB D 4 1984J–DFLASH–06/06 ...

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... Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued) Buffer Read (Opcode: 54H) CS SCK COMMAND OPCODE Status Register Read (Opcode: 57H) CS SCK COMMAND OPCODE HIGH-IMPEDANCE SO 1984J–DFLASH–06/ HIGH-IMPEDANCE AT45DB011B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB MSB 21 ...

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... Detailed Bit-level Read Timing – SPI Mode 0 Continuous Array Read (Opcode: E8H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45DB011B DATA OUT HIGH-IMPEDANCE LSB MSB BIT 2111 BIT PAGE n PAGE n DATA OUT MSB D 4 1984J–DFLASH–06/06 ...

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... Detailed Bit-level Read Timing – SPI Mode 0 (Continued) Buffer Read (Opcode: D4H) CS SCK COMMAND OPCODE Status Register Read (Opcode: D7H) CS SCK HIGH-IMPEDANCE SO 1984J–DFLASH–06/ HIGH-IMPEDANCE COMMAND OPCODE MSB AT45DB011B DATA OUT MSB STATUS REGISTER OUTPUT LSB MSB 23 ...

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... Detailed Bit-level Read Timing – SPI Mode 3 Continuous Array Read (Opcode: E8H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45DB011B DATA OUT HIGH-IMPEDANCE LSB MSB BIT 2111 BIT PAGE n PAGE n DATA OUT MSB D 4 1984J–DFLASH–06/06 ...

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... Detailed Bit-level Read Timing – SPI Mode 3 (Continued) Buffer Read (Opcode: D4H) CS SCK COMMAND OPCODE Status Register Read (Opcode: D7H) CS SCK HIGH-IMPEDANCE SO 1984J–DFLASH–06/ HIGH-IMPEDANCE COMMAND OPCODE AT45DB011B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB MSB ...

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... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB011B 26 START provide address ...

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... BUFFER TRANSFER (53H) (82H) MEMORY PAGE PROGRAM (2) Auto Page Rewrite (58H) INCREMENT PAGE (2) ADDRESS POINTER END PA6 PA5 PA4 AT45DB011B If planning to modify multiple bytes currently stored within a page of the Flash array BUFFER WRITE (84H) BUFFER to MAIN (83H) PA3 PA2 - PA0 Sector ...

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... Wide, Plastic Thin Shrink Small Outline Package (TSSOP) AT45DB011B 28 Ordering Code (1) AT45DB011B-CC AT45DB011B-SC (1) AT45DB011B-XC (1) AT45DB011B-CI AT45DB011B-SI (1) AT45DB011B-XI Ordering Code AT45DB011B-SU (1) AT45DB011B-XU Package Type Package Operation Range 9C1 Commercial 8S2 (0°C to 70°C) 14X 9C1 Industrial 8S2 (-40°C to 85°C) 14X Package Operation Range 8S2 ...

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... REF 1.00 (0.0394) BSC NON-ACCUMULATIVE BOTTOM VIEW TITLE 9C1, 9-ball ( Array 1.2 mm Body, 1.0 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) AT45DB011B SIDE VIEW 0.25(0.010)MIN 1.50(0.059) REF 2.0 (0.079) 0.40 (0.016) DIA BALL TYP DRAWING NO. 9C1 04/11/01 REV ...

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... It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. 5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB011B TOP VIEW ...

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... TITLE 14X (Formerly "14T"), 14-lead (4.4 mm Body) Thin Shrink Small Outline Package (TSSOP) AT45DB011B INDEX MARK 6.50 (0.256) 6.25 (0.246) SEATING PLANE DRAWING NO. 14X 05/16/01 REV. B ...

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