AT26DF161A-SU Atmel, AT26DF161A-SU Datasheet
AT26DF161A-SU
Specifications of AT26DF161A-SU
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AT26DF161A-SU Summary of contents
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... SOIC (150-mil and 208-mil wide) – 8-pad MLF ( 1.00 mm) 1. Description The AT26DF161A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer-based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The ...
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... Specifically designed for use in 3-volt systems, the AT26DF161A supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. ...
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Pin Descriptions and Pinouts Table 2-1. Pin Descriptions Symbol Name and Function CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode ...
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... HOLD 4. Memory Array To provide the greatest flexibility, the memory array of the AT26DF161A can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into phys- ical sectors of various sizes, of which each sector can be individually protected from program and erase operations ...
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... Figure 4-1. Memory Architecture Diagram Internal Sectoring for 64KB Sector Protection Block Erase Function (D8h Command) (52h Command) (20h Command) 64KB 64KB (Sector 31) 64KB 64KB (Sector 30) 64KB 64KB (Sector 0) 3640D–DFLASH–8/09 Block Erase Detail 32KB 4KB Block Erase Block Erase ...
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... Device Operation The AT26DF161A is controlled by a set of instructions that are sent from a host controller, com- monly referred to as the SPI Master. The SPI Master communicates with the AT26DF161A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO) ...
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Table 6-1. Command Listing Command Read Commands Read Array Read Array (Low Frequency) Program and Erase Commands Block Erase (4 Kbytes) Block Erase (32 Kbytes) Block Erase (64 Kbytes) Chip Erase Byte/Page Program (1 to 256 Bytes) Sequential Program Mode ...
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... The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 7-1. Read Array – 0Bh Opcode SCK OPCODE MSB HIGH-IMPEDANCE SO Figure 7-2. Read Array – 03h Opcode CS SCK SI MSB HIGH-IMPEDANCE SO AT26DF161A ADDRESS BITS A23- ...
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... CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be pro- grammed into the memory array. In addition, if the address specified by A23 - A0 points to a memory location within a sector that is in the protected state (see section ...
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... ADh or AFh must be clocked into the device. For the first program cycle, three address bytes must be clocked in after the opcode to designate the first byte location to program. After the address bytes have been clocked in, the byte of data to be programmed can be sent to the AT26DF161A 10 2 ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. If the address initially specified by A23 - A0 points to a memory location within a sector that is in the protected state, then the Sequential Program Mode command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Sta- tus Register will also be reset back to the logical “ ...
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... CS pin is deas- serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. AT26DF161A 12 Status Register Read ...
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... If the address specified by A23 - A0 points to a memory location within a sector that is in the pro- tected state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. In addition, with the larger Block Erase sizes of 32K and 64 Kbytes, more than one physical sector may be erased (e ...
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... The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-6. AT26DF161A 14 . CHPE time to determine if the device has finished erasing. At ...
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Protection Commands and Features 9.1 Write Enable The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Regis- ter to a logical “1” state. The WEL bit must be set before a ...
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... If the Sector Protection Registers are locked, then any attempts to issue the Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Reg- ister back to a logical “0” and return to the idle state once the CS pin has been deasserted. AT26DF161A 16 Write Disable ...
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Figure 9-3. 9.4 Unprotect Sector Issuing the Unprotect Sector command to a particular sector address will reset the correspond- ing Sector Protection Register to the logical “0” state (see Register values). Every physical sector of the device has a corresponding ...
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... Global Unprotect, the same WP and SPRL conditions must be met but the system must write a logical “0” to bits and 2 of the Status Register. necessary for a Global Protect or Global Unprotect to be performed. AT26DF161A 18 page 26 for command execution details). The Write Status Register com- ...
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Table 9-2. WP State Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector Protection Registers are not locked), then writing a 00h to the Status Register will perform a ...
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... Figure 9-5. CS SCK SI SO AT26DF161A 20 for details on the Status Register format and what values can be Read Sector Protection Register – Output Data Sector Protection Register Value Sector Protection Register value is 0 (sector is unprotected). Sector Protection Register value is 1 (sector is protected). ...
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... Protected States and the Write Protect (WP) Pin The WP pin is not linked to the memory array itself and has no direct effect on the protection sta- tus of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection Registers Locked) bit in the Status Register, is used to control the hardware locking mechanism of the device. For hardware locking to be active, two conditions must be met – ...
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... Table 9- AT26DF161A 22 Hardware and Software Locking SPRL Locking SPRL Change Allowed 0 Can be modified from Hardware 1 Locked Locked 0 Can be modified from Software 1 Can be modified from Locked Sector Protection Registers Unlocked and modifiable using the Protect and Unprotect Sector commands. Global Protect and Unprotect can also be performed ...
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Status Register Commands 10.1 Read Status Register The Status Register can be read to determine the device's ready/busy status, as well as the sta- tus of many other functions such as Hardware Locking and Software Protection. The Status Register ...
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... Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have been protected, then the individual Sector Pro- tection Registers can be read with the Read Sector Protection Registers command to determine which sectors are in fact protected. AT26DF161A 24 3640D–DFLASH–8/09 ...
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... Unprotect Sector operation completes successfully or aborts • Byte/Page Program operation completes successfully or aborts • Sequential Program Mode reaches highest unprotected memory location • Sequential Program Mode reaches the end of the memory array • Sequential Program Mode aborts • Block Erase operation completes successfully or aborts • ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Table 10-2. Bit 7 SPRL Figure 10-2. Write Status Register AT26DF161A 26 page 18 for more details. Write Status Register Format Bit 6 ...
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... Product Version Code Hex Bit 0 Value Details 1Fh JEDEC Code: 0001 1111 (1Fh for Atmel) 1 Family Code: 010 (AT26DFxxx series) 46h Density Code: 00110 (16-Mbit) 0 MLC Code: 000 (1-bit/cell technology) 01h Product Version: 00001 (First major revision) 1 Value 1Fh 46h 01h ...
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... The Deep Power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-down mode. AT26DF161A ...
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Figure 11-2. Deep Power-down 11.3 Resume from Deep Power-down In order exit the Deep Power-down mode and resume normal device operation, the Resume from Deep Power-down command must be issued. The Resume from Deep Power-down com- mand is the only ...
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... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. Figure 11-4. Hold Mode CS SCK HOLD AT26DF161A 30 Hold Hold Hold 3640D–DFLASH–8/09 ...
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... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT26DF161A -40°C to 85°C 2.7V to 3.6V Min Typ Max 25 ...
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... EDPD (1) t Chip Select High to Standby Mode RDPD Notes: 1. Not 100% tested (value guaranteed by design and characterization load at 70 MHz load at 66 MHz. 3. Only applicable as a constraint for the Write Status Register command when SPRL = 1 AT26DF161A 32 Min Max Units 70 MHz 33 MHz 6 ...
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Program and Erase Characteristics Symbol Parameter (1) t Page Program Time (256 Bytes Byte Program Time BP (1) t Block Erase Time BLKE (1)(2) t Chip Erase Time CHPE (2) t Write Status Register Time WRSR Note: ...
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... Waveforms Figure 13-1. Serial Input Timing CS t CSLS SCK MSB HIGH-IMPEDANCE SO Figure 13-2. Serial Output Timing CS SCK Figure 13-3. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO AT26DF161A 34 t CSLH t t SCKH SCKL t DH LSB HHH HLS t HLH t CSH t CSHH t CSHS ...
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Figure 13-4. HOLD Timing – Serial Output CS SCK t HHH HOLD SI SO Figure 13-5. WP Timing for Write Status Register Command When SPRL = WPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER OPCODE ...
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... Green Package Options (Pb/Halide-free/RoHS Compliant) f (MHz) Ordering Code SCK AT26DF161A-SSU 70 AT26DF161A-SU AT26DF161A-MU 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.208” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8M1-A 8-pad 1.00 mm Very Thin Micro Lead-frame Package (MLF) ...
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Packaging Information 15.1 8S1 – JEDEC SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. ...
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... Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com AT26DF161A TOP VIEW ...
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MLF Pin TOP VIEW BOTTOM VIEW L Notes: 1. This package conforms to JEDEC reference MO-229, Saw Singulation. 2. The terminal # Laser-marked Feature. ...
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... Revision History Revision Level – Release Date A – November 2006 B – October 2007 C – May 2008 D – August 2009 AT26DF161A 40 History Initial Release Added HOLD to device block diagram. Removed the “Preliminary” status Added ‘For New Designs Use AT25DF161’ Reference on Front Page 3640D– ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...