CY7C1355A-117AC Cypress Semiconductor Corp, CY7C1355A-117AC Datasheet

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... Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05539 Rev. ** PRELIMINARY 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Functional Description The CY7C1355C/CY7C1357C ...

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... WRITE WRITE REGISTRY DRIVERS AND DATA COHERENCY CONTROL LOGIC READ LOGIC SLEEP CONTROL CY7C1355C CY7C1357C MEMORY ARRAY INPUT E O REGISTER MEMORY ARRAY DQs F T DQP DQP INPUT E REGISTER MEMORY ARRAY INPUT E REGISTER Page DQs DQP A DQP B DQP C DQP DQs DQP A DQP B ...

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Pin Configurations DQP DDQ BYTE DDQ ...

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Pin Configurations (continued DDQ DDQ Vss/DNU 14 V ...

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Pin Configurations (continued DDQ DDQ DDQ DDQ ...

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Pin Configurations (continued 288M CE2 C DQP DDQ DDQ DDQ ...

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... Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs ...

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Pin Definitions (continued) Name I/O TDO JTAG serial output Synchronous TDI JTAG serial input Synchronous TMS JTAG serial input Synchronous TCK JTAG-Clock /DNU Ground/DNU SS Document #: 38-05539 Rev. ** PRELIMINARY Description Serial data-out to the JTAG ...

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... WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the address register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers ...

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Interleaved Burst Address Table (MODE = Floating First Second Third Address Address Address A1: A0 A1 Mode Electrical Characteristics Parameter Description I Sleep ...

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Truth Table Address Operation Used Deselect Cycle None Deselect Cycle None Deselect Cycle None Continue Deselect Cycle None READ Cycle External (Begin Burst) READ Cycle Next (Continue Burst) NOP/DUMMY READ External (Begin Burst) ...

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Partial Truth Table for Read/Write Function (CY7C1355C) Read Write No bytes written Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Byte C – (DQ and DQP ) ...

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IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1355C/CY7C1357C incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1355C/CY7C1357Ccontains a TAP controller, ...

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Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO ...

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The user must be aware that the TAP controller clock can only operate at a frequency MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the ...

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TAP Timing Test Clock (TCK) Test Mode Select (TMS) Test Data-In (TDI) Test Data-Out (TDO) TAP AC Switching Characteristics Parameter Clock t TCK Clock Cycle Time TCYC t TCK Clock Frequency TF t TCK Clock HIGH time TH t TCK ...

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TAP AC Test Conditions Input pulse levels ................................................ Input rise and fall time..................................................... 1 ns Input timing reference levels .........................................1.25V Output reference levels.................................................1.25V Test load termination supply voltage.............................1.25V TAP DC Electrical Characteristics And Operating Conditions (0°C < T < ...

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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1355C CY7C1357C Description Describes the version number Reserved for Internal Use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor Indicates the presence register Bit Size (x18 ...

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BGA Boundary Scan Order CY7C1355C (256K x 36) BIT BALL BIT # ...

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BGA Boundary Scan Order CY7C1357C (512K x 18) BIT# BALL BIT# BALL ...

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Boundary Scan Order CY7C1355C (256K x 36) BIT# BALL ID BIT# BALL 10N 39 C10 4 P11 ...

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Boundary Scan Order CY7C1357C (512K x 18) BIT# BALL ID BIT# BALL 10N 39 4 P11 ...

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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on V Relative to GND........ –0.5V to +4.6V ...

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Thermal Resistance Parameter Description Θ Thermal Resistance JA (Junction to Ambient) Θ Thermal Resistance JC (Junction to Case) Capacitance [19] Parameter Description C Input Capacitance IN C Clock Input Capacitance CLK C Input/Output Capacitance I/O AC Test Loads and ...

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Switching Characteristics Over the Operating Range Parameter Description t V (Typical) to the First Access POWER DD Clock t Clock Cycle Time CYC t Clock HIGH CH t Clock LOW CL Output Times t Data Output Valid after CLK Rise ...

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Switching Waveforms [26, 27, 28] Read/Write Waveforms 1 2 CLK t CENS t CENH t CH CEN t CES t CEH CE ADV/ ADDRESS D(A1 ...

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Switching Waveforms (continued) NOP, STALL AND DESELECT Cycles CYC CLK t CENS t CENH t CH CEN t CES t CEH CE ADV/ ADDRESS D(A1 ...

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Switching Waveforms (continued) [30, 31] ZZ Mode Timing CLK ZZ I SUPPLY ALL INPUTS (except ZZ) Outputs (Q) Notes: 30. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. ...

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Ordering Information (continued) Speed (MHz) Ordering Code CY7C1355C-117BZC CY7C1357C-117BZC CY7C1355C-117BZI CY7C1357C-117BZI 100 CY7C1355C-100AC CY7C1357C-100AC CY7C1355C-100AI CY7C1357C-100AI CY7C1355C-100BGC CY7C1357C-100BGC CY7C1355C-100BGI ICY7C1357C-100BGI CY7C1355C-100BZC CY7C1357C-100BZC CY7C1355C-100BZI CY7C1357C-100BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. ...

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Package Diagrams 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05539 Rev. ** PRELIMINARY CY7C1355C CY7C1357C 51-85050-*A Page ...

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Package Diagrams (continued) Document #: 38-05539 Rev. ** PRELIMINARY 119-Lead PBGA ( 2.4 mm) BG119 CY7C1355C CY7C1357C 51-85115-*B Page ...

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... Document #: 38-05539 Rev. ** © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

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Document History Page Document Title: CY7C1355C/CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05539 REV. ECN NO. Issue Date ** 242032 See ECN Document #: 38-05539 Rev. ** PRELIMINARY Orig. of Change RKF New ...