CY7C1361A-117AC Cypress Semiconductor Corp, CY7C1361A-117AC Datasheet - Page 9

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CY7C1361A-117AC

Manufacturer Part Number
CY7C1361A-117AC
Description
IC SRAM 9MBIT 117MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1361A-117AC

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
9M (256K x 36)
Speed
117MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1119
Document #: 38-05259 Rev. *C
Partial Truth Table for Read/Write
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
ZZ Mode Electrical Characteristics
Note:
10. For the X18 product, there are only BWa and BWb.
Read
Read
Write one byte
Write all bytes
Write all bytes
I
t
t
DDZZ
ZZS
ZZREC
Parameter
Function
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Description
GW
[10]
H
H
H
H
L
BWE
H
X
L
L
L
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs
for the duration of t
BWa
X
H
X
L
L
Test Conditions
ZZ > V
ZZ > V
ZZ < 0.2V
DD
DD
– 0.2V
– 0.2V
ZZREC
BWb
,
H
H
X
X
ADSP, and ADSC must remain inactive
L
after the ZZ input returns LOW.
2t
Min.
CYC
BWc
H
H
X
X
L
CY7C1361A
CY7C1363A
2t
Max.
10
CYC
Page 9 of 27
BWd
X
H
H
X
L
Unit
mA
ns
ns

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