CY7C025-25JC Cypress Semiconductor Corp, CY7C025-25JC Datasheet

IC SRAM 128KBIT 25NS 84PLCC

CY7C025-25JC

Manufacturer Part Number
CY7C025-25JC
Description
IC SRAM 128KBIT 25NS 84PLCC
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C025-25JC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
128K (8K x 16)
Speed
25ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1158

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C025-25JC
Manufacturer:
CYPRESS
Quantity:
1 831
Part Number:
CY7C025-25JC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Cypress Semiconductor Corporation
Document #: 38-06035 Rev. **
Features
• True Dual-Ported memory cells which allow
• 4K x 16 organization (CY7C024)
• 4K x 18 organization (CY7C0241)
• 8K x 16 organization (CY7C025)
• 8K x 18 organization (CY7C0251)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: I
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using
• On-chip arbitration logic
• Semaphores included to permit software handshaking
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Available in 84-pin PLCC and 100-pin TQFP
• Pin-compatible and functionally equivalent to
simultaneous reads of the same memory location
Master/Slave chip select when using more than one
device
between ports
IDT7024/IDT7025
CC
= 150 mA (typ.)
3901 North First Street
4K x 16/18 and 8K x 16/18 Dual-Port
Static RAM with Sem, Int, Busy
Functional Description
The CY7C024/0241 and CY7C025/0251 are low-power
CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Var-
ious arbitration schemes are included on the CY7C024/0241
and CY7C025/0251 to handle situations when multiple pro-
cessors access the same piece of data. Two ports are provid-
ed, permitting independent, asynchronous access for reads
and writes to any location in memory. The CY7C024/0241 and
CY7C025/0251 can be utilized as standalone 16-/18-bit du-
al-port static RAMs or multiple devices can be combined in
order to function as a 32-/36-bit or wider master/slave du-
al-port static RAM. An M/S pin is provided for implementing
32-/36-bit or wider memory applications without the need for
separate master and slave devices or additional discrete logic.
Application areas include interprocessor/multiprocessor de-
signs, communications status buffering, and dual-port vid-
eo/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two flags
are provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being accessed
by the other port. The Interrupt Flag (INT) permits communication
between ports or systems by means of a mail box. The semaphores
are used to pass a flag, or token, from one port to the other to indicate
that a shared resource is in use. The semaphore logic is comprised
of eight shared latches. Only one side can control the latch (sema-
phore) at any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power-down feature is controlled
independently on each port by a chip select (CE) pin.
The CY7C024/0241 and CY7C025/0251 are available in
84-pin PLCCs (CY7C024 and CY7C025 only) and 100-pin
Thin Quad Plastic Flatpack (TQFP).
San Jose
CA 95134
Revised September 18, 2001
CY7C024/0241
CY7C025/0251
408-943-2600

Related parts for CY7C025-25JC

CY7C025-25JC Summary of contents

Page 1

... Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. The CY7C024/0241 and CY7C025/0251 are available in 84-pin PLCCs (CY7C024 and CY7C025 only) and 100-pin Thin Quad Plastic Flatpack (TQFP). • 3901 North First Street • ...

Page 2

... I/O –I/O on the CY7C0241/0251 Document #: 38-06035 Rev. ** I/O I/O CONTROL CONTROL MEMORY ADDRESS ARRAY DECODER INTERRUPT CE SEMAPHORE L ARBITRATION M/S CY7C024/0241 CY7C025/0251 R [3] – I/O I/O 8R 15R [2] – I/O I [1] BUSY R (CY7C025/0251) A 12R ADDRESS A 11R DECODER R/W R SEM 7C024–1 R INT R Page ...

Page 3

... I/O 10L 5 I/O 6 11L I/O 12L 7 I/O 13L 8 GND 9 I/O 10 14L I/O 11 15L GND Notes the CY7C025/0251. 12L the CY7C025/0251. 12R Document #: 38-06035 Rev. ** 84-Pin PLCC Top View CY7C024 100-Pin TQFP Top View CY7C024 CY7C024/0241 CY7C025/0251 ...

Page 4

... Top View CY7C0241/0251 Chip Enable Read/Write Enable Output Enable Address Data Bus Input/Output 15/17R Semaphore Enable Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag Master or Slave Select Power Ground CY7C024/0241 CY7C025/0251 INT 65 L BUSY 64 L GND 63 M/S 62 BUSY 61 R INT 60 ...

Page 5

... One Port CE or Com’ – 0.2V Ind V V – 0. 0.2V [7] Active Port Outputs MAX CY7C024/0241 CY7C025/0251 7C024/0241–35 7C024/0241–55 7C025/0251–35 7C025/0251– 170 160 40 30 Ambient Temperature + – + 7C024/0241–15 7C024/0241–25 7C025/0251–15 7C025/0251–25 Min. Typ. Max. Min. Typ. Max. ...

Page 6

... 250 TH OUTPUT C = 30pF (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 90% 10% GND 3 ns CY7C024/0241 CY7C025/0251 7C024/0241–35 7C024/0241–55 7C025/0251–35 7C025/0251–55 Min. Typ. Max. Min. Typ. Max. Unit 2.4 2.4 0.4 2.2 2.2 –0.7 0.8 –0.7 –10 +10 – ...

Page 7

... Document #: 38-06035 Rev. ** [9] 7C024/0241–15 7C024/0241–25 7C025/0251–15 7C025/0251–25 Min. Max. Min. Max less than t and t HZCE LZCE HZOE CY7C024/0241 CY7C025/0251 7C024/0241–35 7C024/0241–55 7C025/0251–35 7C025/0251–55 Min. Max. Min. Max time. SCE is less than t . LZOE Page Unit ...

Page 8

... Max. Min Note –t (actual –t (actual). WDD PWE DDD SD Timing after V reaches the CC Parameter ICC DR1 Note: 17 tested. CY7C024/0241 CY7C025/0251 7C024/0241–35 7C024/0241–55 7C025/0251–35 7C025/0251–55 Max. Min. Max. Min Note Note Data Retention Mode 4.5V 4. – ...

Page 9

... ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE and This waveform cannot be used for semaphore reads SEM = access semaphore CY7C024/0241 CY7C025/0251 t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE t HZCE , SEM = 7C024–14 7C024–15 7C024–16 Page ...

Page 10

... AW [26] t PWE [29] t HZWE t SD [23, 24, 25, 31 SCE LOW CE or SEM and a LOW UB or LB. PWE PWE , SEM = CY7C024/0241 CY7C025/0251 [29] t HZOE LZWE NOTE allow the I/O drivers to turn off and data to be placed on HZWE SD 7C024–17 7C024–18 . PWE Page ...

Page 11

... SPS Document #: 38-06035 Rev. ** [32 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [33, 34, 35] MATCH t SPS MATCH = CE = HIGH CY7C024/0241 CY7C025/0251 OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE 7C024–19 7C024–20 Page ...

Page 12

... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 36 LOW Document #: 38-06035 Rev. ** [36 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C024/0241 CY7C025/0251 BHA t BDD t DDD VALID t WDD 7C024–21 7C024–22 Page ...

Page 13

... BUSY will be asserted. PS Document #: 38-06035 Rev. ** [37] ADDRESS MATCH BLC ADDRESS MATCH BLC [37 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C024/0241 CY7C025/0251 t BHC 7C024–23 t BHC 7C024–24 7C024–25 7C024–26 Page ...

Page 14

... Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE FFF (1FFF CY7C025 R/W L INT R [39] t INS Right Side Clears INT : R ADDRESS R INT R : Right Side Sets INT L ADDRESS WRITE FFE (1FFE CY7C025 R/W R INT L t INS Left Side Clears INT ...

Page 15

... Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the CY7C024/0241 and CY7C025/0251 can function as a master (BUSY pins are outputs slave (BUSY pins are inputs). The CY7C024/0241 and CY7C025/0251 have an automatic power-down feature controlled by CE ...

Page 16

... Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Notes: 40. A and A , 1FFF/1FFE for the CY7C025. 0L–12L 0R–12R 41. If BUSY =L, then no change. R 42. If BUSY =L, then no change. ...

Page 17

... CY7C025–25AC CY7C025–25JC CY7C025–25AI CY7C025–25JI 35 CY7C025–35AC CY7C025–35JC CY7C025–35AI CY7C025–35JI 55 CY7C025–55AC CY7C025–55JC CY7C025–55AI CY7C025–55JI Document #: 38-06035 Rev. ** Package Name Package Type A100 100-Pin Thin Quad Flat Pack J83 84-Lead Plastic Leaded Chip Carrier ...

Page 18

... Ordering Code 15 CY7C0251–15AC 25 CY7C0251–25AC CY7C0251–25AI 35 CY7C0251–35AC CY7C0251–35AI 55 CY7C0251–55AC CY7C0251–55AI Document #: 38-06035 Rev. ** Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack ...

Page 19

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 84-Lead Plastic Leaded Chip Carrier J83 CY7C024/0241 CY7C025/0251 51-85048-A 51-85006-A Page ...

Page 20

... Document Title: CY7C024/0241, CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy Document Number: 38-06035 Issue REV. ECN NO. Date ** 110177 09/29/01 Document #: 38-06035 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00255 to 38-06035 CY7C024/0241 CY7C025/0251 ...

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