CY7C09269A-12AC Cypress Semiconductor Corp, CY7C09269A-12AC Datasheet
CY7C09269A-12AC
Specifications of CY7C09269A-12AC
Available stocks
Related parts for CY7C09269A-12AC
CY7C09269A-12AC Summary of contents
Page 1
... Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Two Flow-Through/Pipelined devices — 16K x 16/18 organization (CY7C09269A/369A) • Three Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100- MHz cycle time • ...
Page 2
... Functional Description The CY7C09269A and CY7C09369A are high-speed synchro- nous CMOS 16K, 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. isters on control, address, and data lines allow for minimal set- up and hold times ...
Page 3
... CY7C09269A CY7C09369A A8R 74 A9R 73 A10R 72 A11R 71 A12R 70 A13R LBR 66 UBR 65 CE0R 64 CE1R 63 CNTRSTR 62 R/WR 61 GND 60 OER 59 FT/PIPER 58 I/O17R 57 GND 56 I/O16R 55 I/O15R 54 I/O14R 53 I/O13R 52 I/O12R 51 I/O11R CY7C09269A CY7C09269A CY7C09369A CY7C09369A - 215 35 0.05 - 195 30 0.05 Page ...
Page 4
... For read operations both Input Voltage ............................................–0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >1100V Latch-Up Current..................................................... >200 mA Operating Range Range Commercial CY7C09269A CY7C09369A AND CE must be asserted MAX –I/O ). 8/9L 15/17L Ambient ...
Page 5
... Com’l. 0.05 0.5 0.05 Com’l. 160 200 145 Description Test Conditions MHz 5.0V CC AND CE 0 CY7C09269A CY7C09369A CY7C09269A CY7C09369A -9 2.4 2.4 0.4 0.4 2.2 2.2 0.8 0.8 10 –10 10 –10 420 215 360 105 35 95 220 145 205 0 ...
Page 6
... Note: 8. Test Conditions pF. Document #: 38-06050 Rev 250 TH OUTPUT (b) Thévenin Equivalent (Load 1) [8] 3.0V GND = 1. Capacitance (pF) (b) Load Derating Curve CY7C09269A CY7C09369A OUTPUT 1.4V TH (c) Three-State Delay (Load 2) (Used for CKLZ including scope and jig) ALL INPUT PULSES 90% 90% 10% 10 ...
Page 7
... Test conditions used are Load 2. 10. This parameter is guaranteed by design, but it is not production tested. Document #: 38-06050 Rev. *A CY7C09269A CY7C09369A [ Min. Max. Min. Max. Min 100 6.5 7.5 12 6 6.5 7 CY7C09269A CY7C09369A -12 Max. Min. Max. Unit 40 33 MHz 67 50 MHz Page ...
Page 8
... CD1 Q n [11, 12, 13, 14 CYC2 t CL2 A A n+1 t CD2 Q t CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09269A CY7C09369A n+2 n+3 t CKHZ Q Q n+1 n OHZ OLZ ...
Page 9
... CL2 CD2 HC CD2 [17, 18, 19, 20 MATCH CD1 CWDD , R/W, CNTEN, and CNTRST = for the left port, which is being written to. IH CY7C09269A CY7C09369A CD2 CKHZ CKLZ CD2 CKHZ CKLZ NO NO MATCH t CD1 VALID >maximum specified, then data is not valid CWDD CCS CKHZ A 5 ...
Page 10
... During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06050 Rev. *A [14, 21, 22, 23 n+1 n CD2 CKHZ Q n READ NO OPERATION [14, 21, 22, 23 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE . IH CY7C09269A CY7C09369A A A n+3 n CKLZ WRITE READ A A n+4 n CKLZ CD2 READ Page CD2 Q n+3 Q n+4 ...
Page 11
... OUT OE Document #: 38-06050 Rev. *A [12, 14, 21, 22 n+1 n CD1 CKHZ NO READ OPERATION [12, 14, 21, 22 n OHZ READ CY7C09269A CY7C09369A n+2 n n+2 t CD1 Q n CKLZ DC WRITE READ A A n+3 n CD1 CKLZ DC WRITE READ A n+4 t CD1 A n+5 t CD1 n+4 Page ...
Page 12
... R/W and CNTRST = Document #: 38-06050 Rev. *A [24] t SAD t SCN t CD2 READ WITH COUNTER [24 n+1 READ WITH COUNTER . IH CY7C09269A CY7C09369A t HAD t HCN Q n+1 n+2 COUNTER HOLD READ WITH COUNTER t t SAD HAD t t SCN HCN Q Q n+2 n+3 COUNTER HOLD Q n+3 READ WITH ...
Page 13
... The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06050 Rev n n+1 n+1 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = V IL CY7C09269A CY7C09369A [25, 26 n+2 n n+2 n+3 n+4 WRITE WITH COUNTER . IH A n+4 ...
Page 14
... SD DATA IN DATA OUT COUNTER RESET Notes: 27 UB, and 28. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06050 Rev. *A [14, 26, 27, 28 WRITE READ ADDRESS 0 ADDRESS 0 CY7C09269A CY7C09369A n READ READ ADDRESS 1 ADDRESS n Page n ...
Page 15
... CNTRST I/O Mode Reset out( out( out( Increment out(n+ CY7C09269A CY7C09369A Operation 17 [32] Deselected [32] Deselected Write IN [34] Read Outputs Disabled Operation Counter Reset to Address 0 Load Address Load into Counter Hold External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation Page ...
Page 16
... Ordering Information 16K x16 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09269A-6AC 7.5 CY7C09269A-7AC 9 CY7C09269A-9AC 12 CY7C09269A-12AC 16K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09369A-6AC 7.5 CY7C09369A-7AC 9 CY7C09369A-9AC 12 CY7C09369A-12AC Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06050 Rev. *A © ...
Page 17
... Document Title: CY7C09269A/CY7C09369A 16K x 16/18 Synchronous Dual Port Static RAM Document Number: 38-06050 Issue REV. ECN NO. Date ** 110202 11/11/01 *A 122300 12/27/02 Document #: 38-06050 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00836 to 38-06050 RBI Power up requirements added to Maximum Ratings Information ...