CY7C138-25JC Cypress Semiconductor Corp, CY7C138-25JC Datasheet - Page 9

• Manufacturer Part Number: CY7C138-25JC
• Description: IC SRAM 32KBIT 25NS 68PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C138-25JC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 32K (4K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Density: 32Kb
• Access Time (max): 25ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 12b
• Package Type: PLCC
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 180mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Word Size: 8b
• Number Of Words: 4K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1445

Switching Waveforms
Notes:
26. I/O
27. Semaphores are reset (available to both ports) at cycle start.
28. If t
Timing Diagram of Read with BUSY (M/S=HIGH)
Timing Diagram of Semaphore Contention
Write Timing with Busy Input (M/S=LOW)
ADDRESS
ADDRESS
DATA
DATA IN
SPS
0R
BUSY
A
BUSY
A
R/W
0R
R/W
= I/O
0L
OUTL
is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
SEM
SEM
R/W
R/W
–A
–A
0L
R
L
2R
R
R
2L
L
R
R
L
L
= LOW (request semaphore); CE
(continued)
t
PS
R
= CE
t
WB
L
= HIGH
t
MATCH
SPS
MATCH
[26, 27, 28]
t
BLA
[20]
MATCH
MATCH
t
WC
t
PWE
9
t
PWE
t
WH
t
WDD
t
VALID
SD
t
DDD
t
HD
t
BHA
t
BDD
CY7C138
CY7C139
VALID
C138-16
C138-15
C138-14