CY7C1360B-166AC Cypress Semiconductor Corp, CY7C1360B-166AC Datasheet
CY7C1360B-166AC
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CY7C1360B-166AC Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-05291 Rev. *C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description The CY7C1360B/CY7C1362B SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK) ...
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... DQP BYTE WRITE DRIVER PIPELINED ENABLE A[1: BURST LOGIC Q0 DQ DQP B, B WRITE DRIVER MEMORY DQ DQP A, A WRITE DRIVER PIPELINED ENABLE CY7C1360B CY7C1362B OUTPUT OUTPUT MEMORY SENSE BUFFERS REGISTERS ARRAY AMPS E OUTPUT OUTPUT SENSE BUFFERS AMPS REGISTERS ARRAY DQP A DQP B DQP C ...
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... V V DDQ DDQ SSQ SSQ SSQ SSQ DDQ DDQ DDQ DDQ SSQ SSQ DQP SSQ SSQ DDQ DDQ DQP CY7C1360B CY7C1362B CY7C1362B 15 16 (512K x 18 CY7C1362B 15 16 (512K x 18 DDQ V 76 SSQ 75 NC DQP SSQ V 70 DDQ DDQ 60 V SSQ 59 DQ ...
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... Pin Configurations (continued DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ Document #: 38-05291 Rev. *C 119-ball BGA (2 Chip Enables with JTAG) CY7C1360B (256K x 36 ADSP CE A ADSC DQP ADV CLK BWE DQP MODE TMS TDI TCK CY7C1362B (512K x 18 ADSP ...
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... DDQ 72M A R MODE NC / 36M 288M CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05291 Rev. *C 165-ball fBGA (3 Chip Enable with JTAG) CY7C1360B (256K x 36 CLK 18M SS TDI TMS CY7C1362B (512K x 18 ...
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... CY7C1360B–Pin Definitions TQFP TQFP 3-Chip 2-Chip Name Enable Enable 37,36,32, 37,36,32 33,34,35, 33,34,35, 43,44,45, 44,45,46, 46,47,48, 47,48,49, 49,50,81, 50,81,82, 82,99,100 92,99,100 93,94,95, 93,94,95 BWE CLK [ ADV Document #: 38-05291 Rev. *C BGA fBGA I/O P4,N4, R6,P6,A2, Input- A2,C2, A10,B2, Synchronous R2,3A, B10,P3,P4, ...
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... CY7C1360B–Pin Definitions TQFP TQFP 3-Chip 2-Chip Name Enable Enable 84 84 ADSP 85 85 ADSC 52,53,56, 52,53,56, DQs, 57,58,59, 57,58,59, DQPs 62,63,68, 62,63,68, 69,72,73, 69,72,73, 74,75,78, 74,75,78, 79,2,3,6,7, 79,2,3,6,7, 8,9,12,13,1 8,9,12,13,1 8,19,22, 8,19,22, 23,24,25, 23,24,25, 28,29,51, 28,29,51, 80,1,30 80,1,30 V 15,41,65, 15,41,65 17,40,67, ...
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... CY7C1360B–Pin Definitions TQFP TQFP 3-Chip 2-Chip Name Enable Enable V 5,10,21,26, 5,10,21,26, SSQ 55,60,71, 55,60,71 4,11,20,27, 4,11,20,27, DDQ 54,61,70, 54,61,70 MODE 31 31 TDO - - TDI - - TMS - - TCK - - NC 14,16,66, 14,16,38, 42,39,38 39,42,43, 66, Document #: 38-05291 Rev. *C (continued) BGA fBGA I I/O Ground A1,F1,J1, C3,C9,D3, I/O Power ...
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... Synchronous - A6 Input- Synchronous F4 B8 Input- Asynchronous G4 A9 Input- Synchronous CY7C1360B CY7C1362B Description Address Inputs used to select one of the 512K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE [ and CE are sampled active the two-bit counter. . Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM ...
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... K5,K6,K7, L5,L6,L7, M5,M6,M7, N4, I/O Ground CY7C1360B CY7C1362B Description Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog- nized ...
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... N2,N7,N10, P6,R1, N5,N11,P1, R5,R7, A1,B11,P2, T1,T4,U6 R2,N6 CY7C1360B CY7C1362B Description Power supply for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation ...
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... Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1360B/CY7C1362B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will three-state the output drivers ...
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... RZZI Document #: 38-05291 Rev. *C Linear Burst Address Table (MODE = GND) Fourth First Address Address , Test Conditions ZZ > V – 0. > V – 0. < 0.2V This parameter is sampled This parameter is sampled CY7C1360B CY7C1362B Second Third Address Address Min. Max CYC 2t CYC 2t CYC 0 Fourth Address ...
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... valid. Appropriate write will be done based on which byte write is active. [A:D] CY7C1360B CY7C1362B L-H Three-State L-H Three-State L-H Three-State L-H Three-State L-H Three-State Three-State L L-H Three-State L L L-H Three-State L L-H Three-State L L-H Three-State L-H Three-State L L-H Three-State L L-H D and Writes may occur only on subsequent clocks ...
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... Partial Truth Table for Read/Write Function (CY7C1360B) Read Read Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Bytes B, A Write Byte C – (DQ and DQP ) C C Write Bytes C, A Write Bytes C, B Write Bytes Write Byte D – (DQ ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1360B/CY7C1362B incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... TAP controller’s capture set-up plus hold time (t The SRAM clock input might not be captured correctly if there PRELOAD portion way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue still CY7C1360B CY7C1362B instructions. Unlike the SAMPLE/PRELOAD plus t ). ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE [10, 11] Over the Operating Range Description /t = 1ns CY7C1360B CY7C1362B TDOV t TDOX UNDEFINED Min. Max Page ...
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... DDQ DDQ DDQ I = 100 µ DDQ V DDQ V DDQ V DDQ V DDQ V DDQ GND < V < DDQ CY7C1360B CY7C1362B 1.25V 50 TDO 20pF O Min. Max. = 3.3V 2.4 = 2.5V 2.0 = 3.3V 2.9 = 2.5V 2.1 = 3.3V 0.4 = 2.5V 0.4 = 3.3V 0.2 = 2.5V 0.2 = 3. ...
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... Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1360B CY7C1362B Description Describes the version number Reserved for Internal Use ...
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... BGA Boundary Scan Order CY7C1360B (256K x 36) BIT BALL Signal BIT # ID Name # 1 CLK BWE ADSC ADSP ADV DQP DQP Document #: 38-05291 Rev. *C BALL Signal BIT# BALL ID ID Name MODE 7 P2 DQP Internal Internal Internal Internal Internal Internal Internal C D2 DQP ...
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... Boundary Scan Order CY7C1360B (256K x 36) BIT# BALL Signal BIT# ID Name 1 B6 CLK BWE ADSC ADSP ADV 43 8 B10 A10 C11 DQP E10 F10 G10 D10 D11 E11 F11 G11 H11 J10 K10 L10 M10 J11 K11 L11 DQ 62 ...
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... V ≤ /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < CY7C1360B CY7C1362B Ambient Temperature V DD 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5% –40°C to +85°C Min. Max. 3.135 3.6 3.135 V DD 2.375 2 ...
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... Test Conditions T = 25° MHz 3.3V 2.5V DDQ R = 317Ω 3.3V OUTPUT 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V OUTPUT =1538Ω INCLUDING JIG AND (b) SCOPE CY7C1360B CY7C1362B TQFP BGA fBGA Package Package Package TQFP BGA fBGA Package Package Package ...
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... DDQ is the time that the power needs to be supplied above V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1360B CY7C1362B 200 MHz 166 MHz Max Min. Max Min 5.0 6 ...
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... OEV OEHZ t OELZ t DOH Q(A2) Q( Q(A1) DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1360B CY7C1362B A3 Burst continued with new base address Deselect cycle t CHZ Q( Q( Q(A2) Q( Burst wraps around to its initial state BURST READ is HIGH LOW HIGH ...
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... Full width Write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05291 Rev WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1360B CY7C1362B ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVS ADVH D( D( ...
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... The data bus (Q) remains in high-Z following a Write cycle, unless a new Read access is initiated by ADSP or ADSC . 25 HIGH. Document #: 38-05291 Rev WES t WEH OELZ D(A3) t OEHZ Q(A2) Single WRITE DON’T CARE UNDEFINED CY7C1360B CY7C1362B A5 D(A5) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ A6 D(A6) Back-to-Back WRITEs Page ...
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... CY7C1360B-225AC CY7C1362B-225AC CY7C1360B-225AI CY7C1362B-225AI CY7C1360B-225AJC CY7C1362B-225AJC CY7C1360B-225AJI CY7C1362B-225AJI CY7C1360B-225BGC CY7C1362B-225BGC CY7C1360B-225BGI CY7C1362B-225BGI CY7C1360B-225BZC CY7C1362B-225BZC CY7C1360B-225BZI CY7C1362B-225BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Document #: 38-05291 Rev ZZI I DDZZ High-Z DON’T CARE ...
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... CY7C1362B-200AC CY7C1360B-200AI CY7C1362B-200AI CY7C1360B-200AJC CY7C1362B-200AJC CY7C1360B-200AJI CY7C1362B-200AJI CY7C1360B-200BGC CY7C1362B-200BGC CY7C1360B-200BGI CY7C1362B-200BGI CY7C1360B-200BZC CY7C1362B-200BZC CY7C1360B-200BZI CY7C1362B-200BZI 166 CY7C1360B-166AC CY7C1362B-166AC CY7C1360B-166AI CY7C1362B-166AI CY7C1360B-166AJC CY7C1362B-166AJC CY7C1360B-166AJI CY7C1362B-166AJI CY7C1360B-166BGC CY7C1362B-166BGC CY7C1360B-166BGI ICY7C1362B-166BGI CY7C1360B-166BZC CY7C1362B-166BZC CY7C1360B-166BZI CY7C1362B-166BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. ...
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... Package Diagrams 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05291 Rev. *C CY7C1360B CY7C1362B 51-85050-A Page ...
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... Package Diagrams (continued) Document #: 38-05291 Rev. *C 119-Lead PBGA ( 2.4 mm) BG119 CY7C1360B CY7C1362B 51-85115-*B Page ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1360B CY7C1362B 51-85122-*C ...
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... Document History Page Document Title: CY7C1360B/CY7C1362B 9-Mbit (256K x 36/512K x 18) Pipelined SRAM Document #: 38-05291 Rev. *C REV. ECN NO. Issue Date ** 114766 08/08/02 *A 117939 08/20/02 *B 205060 See ECN *C 225181 See ECN Document #: 38-05291 Rev. *C Orig. of Change RCS New Data Sheet RCS Added A0 and A1 to 165 fBGA pinout ...