CY7C037V-15AXC Cypress Semiconductor Corp, CY7C037V-15AXC Datasheet

IC SRAM 576KBIT 15NS 100LQFP

CY7C037V-15AXC

Manufacturer Part Number
CY7C037V-15AXC
Description
IC SRAM 576KBIT 15NS 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C037V-15AXC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
576K (32K x 18)
Speed
15ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C037V-15AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C037V-15AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Features
Notes
Cypress Semiconductor Corporation
Document #: 38-06078 Rev. *B
1. CY7C027V, CY7C027VN and CY7C027AV are functionally identical.
2. CY7C037V and CY7C037AV are functionally identical.
3. I/O
4. I/O
5. A
6. BUSY is an output in master mode and an input in slave mode.
True Dual-Ported memory cells which allow
simultaneous access of the same memory location
32K x 16 organization (CY7C027V/027VN/027AV
64K x 16 organization (CY7C028V)
32K x 18 organization (CY7C037V/037AV
64K x 18 organization (CY7C038V)
0.35 micron CMOS for optimum speed and power
High speed access: 15, 20, and 25 ns
Low operating power
Active: I
Standby: I
Logic Block Diagram
0
–A
8
0
–I/O
–I/O
14
for 32K; A
CC
15
7
R/W
UB
CE
CE
OE
I/O
I/O
A
A
CE
OE
R/W
SEM
BUSY
INT
UB
LB
LB
for x16 devices; I/O
0L
0L
SB3
for x16 devices; I/O
L
= 115 mA (typical)
L
0L
1L
8/9L
0L
L
L
L
L
L
–A
–A
L
L
L
–I/O
L
[5]
[5]
L
= 10 μA (typical)
14/15L
14/15L
–I/O
[6]
0
–A
[4]
7/8L
[3]
15/17L
15
for 64K devices.
CE
0
9
–I/O
–I/O
15/16
L
8/9
8/9
8
17
for x18 devices.
for x18 devices.
Address
Decode
15/16
[2]
)
198 Champion Court
Control
[1]
3.3V 32K/64K x 16/18 Dual-Port Static
I/O
)
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
Control
Fully asynchronous operation
Automatic power down
Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Separate upper-byte and lower-byte control
Dual chip enables
Pin select for Master or Slave
Commercial and Industrial temperature ranges
100-pin Pb-free TQFP and 100-pin TQFP
I/O
San Jose
CY7C027V/027VN/027AV/028V
Address
Decode
15/16
,
CA 95134-1709
CY7C037V/037AV/038V
15/16
8/9
8/9
CE
R
I/O
Revised December 09, 2008
8/9L
I/O
A
A
[6]
0R
0R
–I/O
0L
–A
–A
–I/O
[5]
[5]
BUSY
SEM
R/W
15/17R
14/15R
14/15R
CE
CE
R/W
[3]
INT
UB
LB
OE
OE
CE
UB
[4]
LB
7/8R
0R
1R
R
R
R
R
R
R
R
R
R
R
R
R
408-943-2600
RAM
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Related parts for CY7C037V-15AXC

CY7C037V-15AXC Summary of contents

Page 1

... R/W L SEM L [6] BUSY L INT Notes 1. CY7C027V, CY7C027VN and CY7C027AV are functionally identical. 2. CY7C037V and CY7C037AV are functionally identical. 3. I/O –I/O for x16 devices; I/O –I/O for x18 devices I/O –I/O for x16 devices; I/O –I/O for x18 devices –A for 32K ...

Page 2

... I/O14L 21 I/O13L 22 I/O12L 23 I/O11L 24 I/O10L Note 1. This pin is NC for CY7C027V/027VN/027AV. Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V Figure 1. 100-Pin TQFP (Top View CY7C028V (64K x 16 CY7C037V/037AV/038V A9R 74 A10R 73 A11R 72 A12R 71 A13R 70 A14R 69 A15R [ LBR 65 UBR 64 CE0R 63 CE1R 62 SEMR 61 GND 60 R/WR 59 OER 58 GND 57 GND ...

Page 3

... Selection Guide Parameter Maximum Access Time Typical Operating Current Typical Standby Current for I (Both ports TTL level) SB1 Typical Standby Current for I (Both ports CMOS level) SB3 Note 2. This pin is NC for CY7C037V/037AV. Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V Figure 2. 100-Pin TQFP (Top View ...

Page 4

... INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Description ≤ V Chip Enable (CE is LOW when CE 0 ...

Page 5

... If both ports attempt to access the semaphore within t obtained by one side or the other, but there is no guarantee which side and controls the semaphore. CY7C037V/037AV/038V before attempting to read the semaphore. The + t after the rising edge of the SWRD DOE represents the semaphore address ...

Page 6

... Ind. Com’l. 80 120 [3] Ind. Com’l. 10 250 [3] Ind. Com’l. 75 105 [3] Ind. Test Conditions ° MHz 3.3V CC CY7C037V/037AV/038V [2] .................................. –0. Ambient Temperature V CC ° ° 3.3V ± 300 +70 C ° ° 3.3V ± 300 mV – +85 C -20 -25 Unit Typ Max Min ...

Page 7

... CY7C027V/027VN/027AV/028V/ CY7C037V/037AV/038V -15 Min Max less than t and t is less than t HZCE LZCE HZOE CY7C037V/037AV/038V 3. 590Ω OUTPUT 435Ω (c) Three-State Delay (Load 2) (Used for & HZWE LZWE including scope and jig) Unit -20 -25 Min Max Min Max ...

Page 8

... C. This parameter is guaranteed but not tested Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V [6] (continued) CY7C027V/027VN/027AV/028V/ -15 Min Max Timing and during CC reaches the mini- CC Parameter ICC DR1 Figure 11 –t (actual –t (actual). WDD PWE DDD SD CY7C037V/037AV/038V CY7C037V/037AV/038V -20 -25 Min Max Min Max Data Retention Mode 3.0V 3.0V > 2. – ...

Page 9

... Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V t RC DATA VALID t ACE t DOE t LZOE t LZCE [15, 17, 18, 19 LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads access semaphore SEM = CY7C037V/037AV/038V [15, 16, 17] t OHA [15, 18, 19] t HZCE t HZOE DATA VALID OHA t HZCE t HZCE Page [+] Feedback ...

Page 10

... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V [23] t PWE [26] t HZWE SCE LOW CE or SEM and a LOW PWE HZWE . CY7C037V/037AV/038V [20, 21, 22, 23] [26] t HZOE LZWE NOTE [20, 21, 22, 28 allow the I/O drivers to turn off and data to be placed on SD PWE Page [+] Feedback ...

Page 11

... SPS Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V t SAA VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE MATCH t SPS MATCH = HIGH. L CY7C037V/037AV/038V [29] t OHA t ACE DATA VALID OUT t DOE [30, 31, 32] Page [+] Feedback ...

Page 12

... Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Figure 12. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 33 LOW Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V t WC MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C037V/037AV/038V [33 BHA t BDD t DDD VALID Page [+] Feedback ...

Page 13

... BUSY is asserted. PS Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V ADDRESS MATCH BLC ADDRESS MATCH BLC ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C037V/037AV/038V [34] t BHC t BHC [34] Page [+] Feedback ...

Page 14

... R deasserted first 36 depends on which enable pin (CE or R/W INS INR L Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V Figure 15. Interrupt Timing Diagrams t WC [35 READ 7FFF (FFFF for CY7C028V/38V) [36] t INR t WC [35 READ 7FFE (FFFF for CY7C028V/38V) [36] t INR ) is asserted last. L CY7C037V/037AV/038V Page [+] Feedback ...

Page 15

... Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C037V/037AV/038V –I/O Operation 8 Deselected: Power Down Deselected: Power Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only ...

Page 16

... Ordering Code 15 CY7C028V-15AC CY7C028V-15AXC 20 CY7C028V-20AC CY7C028V-20AXC CY7C028V-20AI CY7C028V-20AXI 25 CY7C028V-25AC CY7C028V-25AXC 32K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C037V-15AC CY7C037V-15AXC 20 CY7C037V-20AC CY7C037AV-20AXC 25 CY7C037V-25AC CY7C037V-25AXC 64K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C038V-15AC CY7C038V-15AXC 20 CY7C038V-20AC CY7C038V-20AXC CY7C038V-20AI CY7C038V-20AXI ...

Page 17

... Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06078 Rev. *B CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V 51-85048-*C Page [+] Feedback ...

Page 18

... Added Pb-Free packaging information. 12/17/08 Added CY7C027VN, CY7C027AV and CY7C037AV parts Updated Ordering information table PSoC Solutions General psoc.cypress.com Low Power/Low Voltage clocks.cypress.com Precision Analog LCD Drive CAN 2.0b image.cypress.com USB Revised December 09, 2008 CY7C037V/037AV/038V psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page [+] Feedback ...

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