CY7C09389V-6AXC Cypress Semiconductor Corp, CY7C09389V-6AXC Datasheet - Page 9

• Manufacturer Part Number: CY7C09389V-6AXC
• Description: IC SRAM 1.152MBIT 6.5NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09389V-6AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 1.152M (64K x 18)
• Speed: 6.5ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Notes
Document #: 38-06056 Rev. *C
21. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
22. UB, LB, OE and ADS = V
23. The same waveforms apply for a right port write to flow through left port read.
24. CE
25. OE = V
26. It t
ADDRESS
ADDRESS
DATA
DATA
ADDRESS
t
CCS
ADDRESS
ADDRESS
DATA
CCS
0
, UB, LB, and ADS = V
+ t
DATA
CE
CE
OUT(B2)
OUT(B1)
≤ maximum specified, then data from right port READ is not valid until the maximum specified for t
IL
CD1
CLK
CLK
R/ W
CLK
R/ W
OUTR
for the Right Port, which is being read from. OE = V
0(B1)
0(B2)
(B1)
(B1)
(B2)
. t
INL
CWDD
L
R
R
R
L
L
L
= ADDRESS
t
t
does not apply in this case.
t
t
SA
SC
SA
SC
IL
t
t
t
; CE
IL
SW
SA
SD
(B2)
; CE
A
A
0
0
.
1(B1)
Figure 8. Left Port Write to Flow Through Right Port Read
t
1
CH2
MATCH
, CNTEN, and CNTRST = V
VALID
, CE
(continued)
t
t
t
t
SW
SA
MATCH
t
t
t
t
CYC2
CCS
HA
HC
HA
HC
1(B2)
t
DC
, R/W, CNTEN, and CNTRST = V
t
CL2
t
t
t
t
HW
HA
t
HW
HA
HD
Figure 7. Bank Select Pipelined Read
A
A
1
1
t
CWDD
t
CD2
t
CD1
IH
IH
for the Left Port, which is being written to.
.
t
SC
D
t
0
SC
A
A
2
2
t
t
DC
HC
IH
.
t
HC
t
CD2
MATCH
NO
VALID
D
MATCH
A
A
1
3
NO
3
t
DC
t
t
CKLZ
[21, 22]
CKHZ
CWDD
t
t
CD2
DC
. If t
[23, 24, 25, 26]
CCS
CY7C09269V/79V/89V
CY7C09369V/79V/89V
t
>maximum specified, then data is not valid until
CD1
D
A
A
4
2
4
t
t
t
CKHZ
CD2
CKLZ
D
3
A
A
VALID
5
t
5
CKLZ
t
t
CKHZ
CD2
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D
4
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