CY7C1021B-12ZXCT Cypress Semiconductor Corp, CY7C1021B-12ZXCT Datasheet

IC SRAM 1MBIT 12NS 44TSOP

CY7C1021B-12ZXCT

Manufacturer Part Number
CY7C1021B-12ZXCT
Description
IC SRAM 1MBIT 12NS 44TSOP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1021B-12ZXCT

Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
1M (64K x 16)
Speed
12ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
44-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Cypress Semiconductor Corporation
Document #: 38-05145 Rev. *C
Features
Functional Description
The CY7C1021B is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
• Temperature Ranges
• High speed
• CMOS for optimum speed/power
• Low active power
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in Pb-free and non Pb-free 44-pin TSOP II and
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
— t
— t
— 770 mW (max.)
44-pin 400-mil-wide SOJ
AA
AA
= 12 ns (Commercial & Industrial)
= 15 ns (Automotive)
A
A
A
A
A
A
A
A
5
4
3
2
1
0
7
6
[1]
DATA IN DRIVERS
COLUMN DECODER
512 X 2048
RAM Array
64K x 16
198 Champion Court
automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021B is available in standard 44-pin TSOP Type II
and 44-pin 400-mil-wide SOJ packages.
1-Mbit (64K x 16) Static RAM
15
San Jose
). If Byte High Enable (BHE) is LOW, then data
9
through I/O
,
CA 95134-1709
1
to I/O
I/O
I/O
1
BHE
WE
CE
OE
BLE
1
9
through I/O
–I/O
–I/O
8
. If Byte High Enable (BHE) is
16
0
Revised September 28, 2006
) is written into the location
through A
8
16
16
CY7C1021B
) are placed in a
1
15
through I/O
).
9
408-943-2600
to I/O
16
. See
8
), is
0
[+] Feedback

Related parts for CY7C1021B-12ZXCT

CY7C1021B-12ZXCT Summary of contents

Page 1

... HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021B is available in standard 44-pin TSOP Type II and 44-pin 400-mil-wide SOJ packages. DATA IN DRIVERS 64K x 16 ...

Page 2

... When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system. Power Supply Power Supply inputs to the device. CY7C1021B -12 - 140 130 ...

Page 3

... CC CC 0.3V, V > V – 0.3V Auto or V < 0.3V Version Test Conditions T = 25° MHz 5.0V CC Test Conditions CY7C1021B Ambient [3] Temperature ( ± 10% 0°C to +70°C 5V ± 10% –40°C to +85°C 5V ± 10% –40°C to +125°C -12 -15 Min. Max. Min. Max. Unit 2 ...

Page 4

... Rise Time: 1 V/ns Rise Time: 1 V/ns (b) (b) 167 167 1.73V 1.73V [5] 7C1021B-12 Min [ [ [ less than less than t , and t HZCE LZCE HZOE LZOE HZWE CY7C1021B ALL INPUT PULSES ALL INPUT PULSES 90% 90% 90% 90% 10% 10% 10% 10% Fall Time: 1 V/ns 7C1021B-15 Max. Min. Max. Unit ...

Page 5

... CURRENT Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = V 10 HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05145 Rev OHA t RC DOE DATA VALID 50 CY7C1021B DATA VALID t HZOE t HZCE t HZBE HIGH IMPEDANCE ICC CC 50% I ISB SB ...

Page 6

... Write Cycle No. 2 (BLE or BHE Controlled) ADDRESS t SA BHE, BLE WE CE DATA I/O Notes: 12. Data I/O is high impedance BHE and/or BLE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05145 Rev SCE PWE PWE t SCE CY7C1021B Page [+] Feedback ...

Page 7

... L Data Data High High High Z Ordering Information Speed (ns) Ordering Code 12 CY7C1021B-12VC CY7C1021B-12VXC CY7C1021B-12ZC CY7C1021B-12ZXC CY7C1021B-12VI CY7C1021B-12VXI Document #: 38-05145 Rev SCE PWE HZWE SD –I/O I/O –I High Z Power-Down Data Out Read - All bits High Z Read - Lower bits only Data Out Read - Upper bits only ...

Page 8

... Ordering Information (continued) Speed (ns) Ordering Code 15 CY7C1021B-15VC CY7C1021B-15VXC CY7C1021B-15ZC CY7C1021B-15ZXC CY7C1021B-15VI CY7C1021B-15VXI CY7C1021B-15ZI CY7C1021BL-15ZI CY7C1021B-15ZXI CY7C1021BL-15ZXI CY7C1021B-15VE CY7C1021B-15VXE CY7C1021B-15ZE CY7C1021B-15ZSXE Package Diagrams 44 1 1.120 1.130 0.095 0.115 0.023 0.045 0.033 MAX. 0.013 0.023 Document #: 38-05145 Rev. *C Package Name Package Type 51-85082 ...

Page 9

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 44-Pin TSOP II (51-85087) CY7C1021B 51-85087-*A Page ...

Page 10

... Document History Page Document Title: CY7C1021B 1-Mbit (64K x 16) Static RAM Document Number: 38-05145 Orig. of REV. ECN NO. Issue Date Change ** 109889 09/22/01 *A 238454 See ECN *B 361795 See ECN *C 505726 See ECN Document #: 38-05145 Rev. *C Description of Change SZV Change from Spec number: 38-00951 to 38-05145 ...

Related keywords