CY7C138-15JXC Cypress Semiconductor Corp, CY7C138-15JXC Datasheet - Page 5

• Manufacturer Part Number: CY7C138-15JXC
• Description: IC SRAM 32KBIT 15NS 68PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C138-15JXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 32K (4K x 8)
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-06037 Rev. *B
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
10. At any given temperature and voltage condition for any given device, t
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
15. t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
WDD
DDD
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
READ CYCLE
WRITE CYCLE
BUSY TIMING
Parameter
[12]
[12]
I
OI
BDD
[13]
[15]
[13]
[10,11,12]
[10,11,12]
/I
[10,11,12]
[10,11,12]
[11,12]
[11,12]
OH
is a calculated parameter and is the greater of t
and 30-pF load capacitance.
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Data Valid
[14]
Description
Over the Operating Range
WDD
– t
PWE
(actual) or t
Min.
15
15
12
12
12
10
13
3
3
3
0
2
0
0
3
5
0
7C138-15
7C139-15
HZCE
Note 15
[9]
Max.
is less than t
DDD
15
15
10
10
10
15
10
30
25
15
15
15
15
– t
SD
Min.
(actual).
20
20
25
25
20
15
20
LZCE
3
3
3
0
2
3
5
0
0
0
7C138-25
7C139-25
and t
Note 15
Max.
HZOE
25
25
15
15
15
25
15
50
30
20
20
20
20
is less than t
Min.
35
35
30
30
25
15
30
3
3
3
0
2
0
0
3
5
0
7C138-35
7C139-35
LZOE
Note 15
Max.
35
35
20
20
20
35
20
60
35
20
20
20
20
.
Min.
55
55
40
40
30
20
40
3
3
3
0
2
0
0
3
5
0
7C138-55
7C139-55
CY7C138
CY7C139
Note 15
Max.
Page 5 of 16
55
55
25
25
25
55
25
70
40
45
40
40
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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