CY7C1512AV18-250BZI Cypress Semiconductor Corp, CY7C1512AV18-250BZI Datasheet
CY7C1512AV18-250BZI
Manufacturer Part Number
CY7C1512AV18-250BZI
Description
IC SRAM 72MBIT 250MHZ 165TFBGA
Manufacturer
Cypress Semiconductor Corp
Datasheets
1.CY7C1514AV18-167BZXC.pdf
(28 pages)
2.CY7C1512AV18-200BZXC.pdf
(26 pages)
3.CY7C1512AV18-200BZXC.pdf
(24 pages)
4.CY7C1514AV18-200BZXI.pdf
(28 pages)
Specifications of CY7C1512AV18-250BZI
Format - Memory
RAM
Memory Type
SRAM - Synchronous, QDR II
Memory Size
72M (4M x 18)
Speed
250MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
-40°C ~ 85°C
Package / Case
165-TFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1512AV18-250BZI
Manufacturer:
CYPRESS
Quantity:
490
Company:
Part Number:
CY7C1512AV18-250BZI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C1512AV18-250BZIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Features
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Selection Guide
Cypress Semiconductor Corporation
Document #: 001-06984 Rev. *C
Maximum Operating Frequency
Maximum Operating Current
Separate independent read and write data ports
❐
250 MHz clock for high bandwidth
2-word burst on all accesses
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 500 MHz) at 250 MHz
Two input clocks (K and K) for precise DDR timing
❐
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR-II operates with 1.5 cycle read latency when Delay Lock
Loop (DLL) is enabled
Operates as a QDR-I device with 1 cycle read latency in DLL
off mode
Available in x 8, x 9, x 18, and x 36 configurations
Full data coherency, providing most current data
Core V
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Supports concurrent transactions
SRAM uses rising edges only
DD
= 1.8V (±0.1V); IO V
Description
DDQ
x18
x36
= 1.4V to V
x8
x9
•
198 Champion Court
250 MHz
DD
1230
1240
1350
1560
250
72-Mbit QDR™-II SRAM 2-Word
Configurations
CY7C1510AV18 – 8M x 8
CY7C1525AV18 – 8M x 9
CY7C1512AV18 – 4M x 18
CY7C1514AV18 – 2M x 36
Functional Description
The CY7C1510AV18, CY7C1525AV18, CY7C1512AV18, and
CY7C1514AV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR-II archi-
tecture has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus that exists with
common IO devices. Access to each port is through a common
address bus. Addresses for read and write addresses are
latched on alternate rising edges of the input (K) clock. Accesses
to the QDR-II read and write ports are completely independent
of one another. To maximize data throughput, both read and write
ports are equipped with DDR interfaces. Each address location
is associated with two 8-bit words (CY7C1510AV18), 9-bit words
(CY7C1525AV18), 18-bit words (CY7C1512AV18), or 36-bit
words (CY7C1514AV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus turn-arounds.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
200 MHz
1005
1015
1105
1280
200
•
CY7C1510AV18, CY7C1525AV18
CY7C1512AV18, CY7C1514AV18
San Jose
,
CA 95134-1709
167 MHz
Burst Architecture
1090
167
850
860
935
Revised September 27, 2007
•
408-943-2600
MHz
Unit
mA
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