M24C64-WMN6P STMicroelectronics, M24C64-WMN6P Datasheet
M24C64-WMN6P
Specifications of M24C64-WMN6P
M24C64-WMN6P
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M24C64-WMN6P Summary of contents
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... Random and Sequential Read modes ■ Write protect of the whole memory array ■ Single supply voltage: – M24C64-W: 2 5.5 V – M24C64-R: 1 5.5 V – M24C64-xF: 1 5.5 V ■ Enhanced ESD/Latch-Up protection ■ More than 1 million Write cycles ■ More than 40-year data retention ■ ...
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... Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9 Write Identification Page (M24C64-D only 4.10 Lock Identification Page (M24C64-D only 4.11 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . . . 18 4.12 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19 4.13 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.14 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F 4.16 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.17 Read Identification Page (M24C64- 4.18 Read the lock status (M24C64- 4.19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ...
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... TSSOP8 – 8 lead thin shrink small outline, package mechanical data Table 21. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 22. WLCSP-R 5-bump wafer-length chip-scale package mechanical data . . . . . . . . . . . . . . . 37 Table 23. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 24. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Doc ID 16891 Rev 23 ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. WLCSP connections (top view Figure 4. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Figure Fast mode (f C capacitance (C bus 2 Figure Fast mode Plus (f parasitic capacitance (C 2 Figure bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 9 ...
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... M24C64-x and M24C64-DF devices are I2C-compatible electrically erasable programmable memories (EEPROM). They are organized as 8192 × 8 bits. The M24C64-D also offers an additional page, named the Identification Page (32 bytes) which can be written and (later) permanently locked in Read-only mode. This Identification Page offers flexibility in the application board production line can be used to store unique identification parameters and/or parameters specific to the production line ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F Table 1. Signal names Signal name E2, E1, E0 SDA SCL Figure 2. 8-pin package connections 1. See Package mechanical data Figure 3. WLCSP connections (top view) Note: Inputs E2, E1, E0 are internally connected to (001). Please refer to explanations. Function Chip Enable Serial Data Serial Clock ...
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... Control (WC) is driven high. When unconnected, the signal is internally read as V Write operations are allowed. When Write Control (WC) is driven high, device select and Address bytes are acknowledged, Data bytes are not acknowledged. 8/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F indicates how the value of the pull-up resistor can be calculated M24xxx ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F 2.5 V ground the reference for the V SS 2.6 Supply voltage (V 2.6.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V Table 9). In order to secure a stable DC supply voltage recommended to decouple the ...
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... Figure Fast mode Plus (f parasitic capacitance (C 100 Bus line capacitor (pF) 10/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F = 400 kHz): maximum bus When time constant must be below the 400 ns time constant line represented on the left 100 1000 Bus line capacitor (pF MHz): maximum R ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F 2 Figure bus protocol SCL SDA SCL SDA Start Condition SCL SDA Table 2. Device select code Device select code 1. The most significant bit, b7, is sent first. 2. E2, E1 and E0 are compared against the respective external pins on the memory device. ...
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... Memory organization 3 Memory organization The memory is organized as shown in Figure 8. Block diagram SCL SDA 12/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Figure 8. Control Logic I/O Shift Register Address Register and Counter Doc ID 16891 Rev 23 High Voltage Generator Data Register 1 Page X Decoder AI06899 ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F 4 Device operation The device supports the I data on to the bus is defined transmitter, and any device that reads the data receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization ...
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... Standby mode. Table 5. Operating modes Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write Only one M24C64 in WLCSP package can be connected on the I²C bus (see 14/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F (1) RW bit WC Bytes ≥ ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F Figure 9. Write mode sequences with (data write inhibited) WC Byte Write WC Page Write WC (cont'd) Page Write (cont'd) ACK ACK Dev select Byte address Byte address R/W ACK ACK Dev select Byte address Byte address R/W NO ACK NO ACK Data in N ...
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... NoAck. After each byte is transferred, the internal byte address counter (inside the page) is incremented. The transfer is terminated by the bus master generating a Stop condition. 16/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F , and the successful completion of a Write operation, W Figure ...
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... Page Write (cont'd) 4.9 Write Identification Page (M24C64-D only) The Identification Page (32 bytes additional page which can be written and (later) permanently locked in Read-only mode. The Identification Page is written by issuing an Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences: ● ...
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... ECC (Error Correction Code) and Write cycling The M24C64 devices identified with the process letter offer an ECC (Error Correction Code) logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC result single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC detects it and replaces it by the correct value ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F Figure 11. Write cycle polling flowchart using ACK First byte of instruction with already decoded by the device 4.12 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t ...
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... Read Sequential Current Read Sequential Random Read 1. The seven most significant bits of the device select code of a Random Read (in the 1 be identical. 20/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F ACK NO ACK Dev select Data out R/W ACK ACK Dev select * Byte address Byte address ...
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... Read Identification Page (M24C64-D) The Identification Page (32 bytes additional page which can be written and (later) permanently locked in Read-only mode. The Identification Page can be read by issuing an Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b ...
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... Device operation 4.18 Read the lock status (M24C64-D) The locked/unlocked status of the Identification page can be checked by issuing a specific truncated command [Identification Page Write instruction + one data byte]: this data byte will be acknowledged if the Identification page is unlocked, while it will not be acknowledged if the Identification page is locked. ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F 5 Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 6 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied ...
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... SCL input rise/fall time, SDA input fall time Input levels Input and output timing reference levels Figure 13. AC test measurement I/O waveform Input Levels 0.8V CC 0.2V CC 24/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Parameter Parameter Parameter Parameter Timing Reference Levels Doc ID 16891 Rev 23 Min. ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F Table 11. Input parameters Symbol C Input capacitance (SDA Input capacitance (other pins) IN Input impedance ( (E2, E1, E0, WC) Input impedance ( (E2, E1, E0, WC) 1. Characterized value, not tested in production. 2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition). (1) Parameter Test condition V < ...
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... Characterized value, not tested in production. 3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle t 4. The new M24C64-W devices (identified by the process letter K) offer I 26/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Test conditions (see ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F Table 13. DC characteristics (M24xxx-W - device grade 3) Symbol Parameter Input leakage current I (SCL, SDA, E2, E1, LI E0) Output leakage I LO current I Supply current (Read Supply current (Write) During t CC0 Standby supply I CC1 current Input low voltage V IL (SCL, SDA, WC) ...
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... Table 12 2. Only for devices operating Characterized value, not tested in production. 4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle t 28/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F (1) Test conditions to those in Table 8 Table ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F Table 15. DC characteristics (M24xxx-F) Symbol Parameter Input leakage current I LI (E1, E2, SCL, SDA) I Output leakage current LO I Supply current (Read Supply current (Write) CC0 I Standby supply current CC1 Input low voltage V IL (SCL, SDA, WC) Input high voltage ...
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... I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when f < 400 kHz The new M24C64 device (identified by the process letter K) offers t (min), while the current device offers t safe margin compared to the avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA ...
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... NS 1. Only M24C64 and M24C64-D devices identified by the process letter K are qualified at 1 MHz. 2. Test conditions (in addition to those in 3. There is no min. or max. values for the input signal rise and fall times however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when f < ...
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... DC and AC parameters Figure 14. AC waveforms 32/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Doc ID 16891 Rev 23 ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 15. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline 1 ...
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... SO8 narrow – 8 lead plastic small outline, 150 mils body width, package mechanical data Symbol ccc Values in inches are converted from mm and rounded to 4 decimal digits. 34/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F A ccc millimeters Typ Min Max 1.75 0.10 0.25 1.25 0.28 ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F Figure 17. TSSOP8 – 8 lead thin shrink small outline, package outline Drawing is not to scale. Table 20. TSSOP8 – 8 lead thin shrink small outline, package mechanical data Symbol α 1. Values in inches are converted from mm and rounded to 4 decimal digits millimeters Typ ...
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... (2) eee 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 36/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F millimeters Typ Min Max 0.550 0.450 0.600 0.020 0.000 0.050 ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F Figure 19. WLCSP-R 5-bump wafer-length chip-scale package outline 1. Drawing is not to scale. Table 22. WLCSP-R 5-bump wafer-length chip-scale package mechanical data Symbol ( (number of terminals) aaa eee 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension measured at the maximum bump diameter parallel to primary datum Z. ...
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... Halogen-free). 3. Used only for device grade 3 and WLCSP packages. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 38/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F M24C64-D (2) (2) ® (RoHS compliant) ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F 10 Revision history Table 24. Document revision history Date Revision 22-Dec-1999 28-Jun-2000 31-Oct-2000 20-Apr-2001 16-Jan-2002 02-Aug-2002 04-Feb-2003 27-May-2003 22-Oct-2003 01-Jun-2004 04-Nov-2004 05-Jan-2005 TSSOP8 package in place of TSSOP14 ( OrderingInfo, 2.3 PackageMechData). 2.4 TSSOP8 package data corrected References to Temperature Range 3 removed from Ordering Information 2 ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F Document converted to new ST template. M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed. M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added. Section 2.3: Chip Enable (E2, E1, E0) (WC) modified, Section 2.6: Supply voltage (VCC) Power On Reset: VCC Lock-Out Write Protect ...
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... Section 2.6.4: Power-down conditions Supply voltage (VCC). Updated Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance Replace M24128 and M24C64 by M24128-BFMB6 and M24C64-FMB6, respectively, in Section 4.9: ECC (error correction code) and write cycling. Added temperature grade 6 in F). ...
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... Revision 10-Dec-2009 05-Feb-2010 15-Sep-2010 16-Nov-2010 08-Dec-2010 42/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F 32 and 128 Kbit densities removed. ECOPACK status of packages specified Ordering information scheme. Section 2.6.2: Power-up conditions Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) ...
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... M24C64-DF, M24C64-W, M24C64-R, M24C64-F Table 24. Document revision history (continued) Date Revision 14-Mar-2011 07-Apr-2011 Updated information concerning E2, E1, E0 for the WLCSP package: – note under Figure 3: WLCSP connections (top view) 22 – comment under Figure 4: Device select code (3) – note under Table 2: Device select code ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 44/44 M24C64-DF, M24C64-W, M24C64-R, M24C64-F Please Read Carefully: © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies www ...