M45PE80-VMN6TP NUMONYX, M45PE80-VMN6TP Datasheet - Page 31

• Manufacturer Part Number: M45PE80-VMN6TP
• Description: IC FLASH 8MBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE80-VMN6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Package: 8SOIC N
• Cell Type: NOR
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 64KByte x 16
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M45PE80-VMN6TPCT

7
Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while V
than the POR threshold value, V
respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program
(PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of t
elapsed after the moment that V
operation of the device is not guaranteed if, by this time, V
Write, Program or Erase instructions should be sent until the later of:
These values are specified in
If the delay, t
selected for READ instructions even if the t
As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration
of the Power-up and Power-down phases.
At Power-up, the device is in the following state:
Normal precautions must be taken for supply rail decoupling, to stabilize the V
device in a system should have the V
package pins. (Generally, this capacitor is of the order of 100 nF).
At Power-down, when V
value, V
(The designer needs to be aware that if a Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption can result.)
V
V
t
t
The device is in the Standby mode (not the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
The Write In Progress (WIP) bit is reset.
PUW
VSL
CC
SS
WI
(min) at Power-up, and then for a further delay of t
at Power-down
after V
after V
, all operations are disabled and the device does not respond to any instruction.
VSL
CC
, has elapsed, after V
CC
passed the V
passed the V
CC
drops from the operating voltage, to below the POR threshold
Table
CC
CC
WI
CC
) until V
WI
Section 3: SPI
– all operations are disabled, and the device does not
(min) level
rises above the V
6.
threshold
CC
CC
rail decoupled by a suitable capacitor close to the
has risen above V
CC
PUW
reaches the correct value:
delay is not yet fully elapsed.
modes.
WI
threshold. However, the correct
CC
CC
VSL
is still below V
(min), the device can be
CC
CC
(min). No
CC
PUW
feed. Each
is less
has
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