DS2430A Maxim Integrated Products, DS2430A Datasheet
DS2430A
Specifications of DS2430A
Available stocks
Related parts for DS2430A
DS2430A Summary of contents
Page 1
... Directly connects to a single port pin of a microprocessor and communicates 15.3kbits per second 8-bit family code specifies DS2430A communication requirements to reader Presence detector acknowledges when reader first applies voltage Low cost TO-92 or 6-pin TSOC and UCSP surface mount package ...
Page 2
... LASERED ROM Each DS2430A contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code (14h). The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (Figure 3) ...
Page 3
... DS2430A BLOCK DIAGRAM Figure DS2430A ...
Page 4
... HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 64-BIT LASERED ROM Figure 3 8-Bit CRC Code MSB LSB MSB 1-WIRE CRC GENERATOR Figure 4 48-Bit Serial Number LSB MSB Polynomial = DS2430A 8-Bit Family Code (14H) LSB ...
Page 5
... After issuing the Write Scratchpad command, the master must first provide a 1-byte address, followed by the data to be written to the scratchpad for the data memory. The DS2430A automatically increments the address after every byte it receives. After having received a data byte for address 1Fh, the address counter wraps around to 00h for the next byte and writing continues until the master sends a Reset Pulse ...
Page 6
... The DS2430A automatically increments the address after every byte read by the master. After the data of address 1Fh has been read, the address counter wraps around to 00h for the next byte and reading continues until the master sends a Reset Pulse ...
Page 7
... After issuing the command code, the master must provide a 1-byte address, followed by the data to be written. The DS2430A automatically increments the address after every byte it receives. After receiving the data byte for address 07h, the address counter wraps around to 00h for the next byte and writing continues until the master sends a Reset Pulse ...
Page 8
... READ APPLICATION REGISTER [C3h] This command is used to read the application register or the register scratchpad. As long as the application register is not yet locked, the DS2430A transmits data from the register scratchpad. After the application register is locked the DS2430A transmits data from the application register, making the register scratchpad inaccessible for reading ...
Page 9
... The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances, the DS2430A is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal type and timing) ...
Page 10
... ROM FUNCTIONS FLOW CHART Figure DS2430A ...
Page 11
... Reset Pulse transmitted by the bus master followed by a Presence Pulse(s) transmitted by the slave(s). The Presence Pulse lets the bus master know that the DS2430A is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence pulse, it can issue one of the four ROM function commands ...
Page 12
... DS2430A when determining a logical level, not triggering any events. Figure 9 shows the initialization sequence required to begin any communication with the DS2430A. A Reset Pulse followed by a Presence Pulse indicates the DS2430A is ready to receive data, given the correct ROM and memory function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for t After the bus master has released the line it goes into Receive mode ...
Page 13
... For a Write-0 time slot, the voltage on the data line must stay below W1LMAX the V threshold until the Write-0 low time t TH voltage on the data line should not exceed V threshold has been crossed, the DS2430A needs a recovery time t slot. READ/WRITE TIMING DIAGRAM Figure 10 Write-1 Time Slot t V ...
Page 14
... DS2430A starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS2430A does not hold the data line low at all, and the voltage starts rising as soon ...
Page 15
... Issue “Copy Scratchpad” command A5h Validation key Data line must be above V Reset pulse Presence pulse CCh Issue “Skip ROM” command F0h Issue “Read Memory” command 00h Start address = 00h Read EEPROM data page Reset pulse Presence pulse DS2430A COMMENTS for t . PUPmin PROG ...
Page 16
... DS2430A -0.5V to +6.0V 20mA -40°C to +85°C +150°C -55°C to +125°C +300°C +260°C (TSOC) +250°C (TO-92) = -40°C to +85°C; see Note 1.) ...
Page 17
... Note 14: Defines maximum possible bit rate. Equal to 1/(t Note 15: Interval after t during which a bus master is guaranteed to sample a logic-0 on DATA if there is a DS2430A RSTL present. Minimum limit is t Note 16: in Figure 10 represents the time required for the pullup circuitry to pull the voltage on DATA up from V V ...
Page 18
... For the latest package outline information and land patterns www.maxim-ic.com/packages. Note that a “+”, “#”, or “-“ in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 3 TO-92 (Bulk) 3 TO-92 (T&R) 6 TSOC PACKAGE CODE Q3+1 Q3+4 D6 DS2430A DOCUMENT NO. 21-0248 21-0250 21-0382 ...
Page 19
... V in Note 6. CC PUP and contradicting t spec from EC table PDL PROG range, corrections in the Memory Functions Example PUP specifications without notice at any time © 2010 Maxim Integrated Products DS2430A PAGES CHANGED — specification IHmax may have to be Various Various revised DD PUP OP Various ...