DS2746G+T&R Maxim Integrated Products, DS2746G+T&R Datasheet - Page 3

• Manufacturer Part Number: DS2746G+T&R
• Description: IC MON BATTERY 2-WIRE 10-TDFN
• Manufacturer: Maxim Integrated Products

Specifications of DS2746G+T&R

• Function: Fuel, Gas Gauge/Monitor
• Battery Type: Lithium-Ion (Li-Ion); Nickel-Metal Hydride (NiMH)
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-WFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(V
SCL, SDA
Input Capacitance:
SCL, SDA
Bus Low Timeout
SCL Clock Frequency
Bus Free Time Between a
STOP and START Condition
Hold Time (Repeated)
START Condition
Low Period of SCL Clock
High Period of SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and
SCL Signals
Fall Time of Both SDA and
SCL Signals
Setup Time for STOP
Condition
Spike Pulse Widths
Suppressed by Input Filter
Capacitive Load for Each Bus
Line
SCL, SDA Input Capacitance
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
DD
= 2.5V to 4.5V, T
PARAMETER
All voltages are referenced to V
Offset specified after auto-calibration cycle and Current Offset Bias register = 0x00.
The DS2746 enters the sleep mode 1.5s to 2.2s after ( SCL < V
Timing must be fast enough to prevent the DS2746 from entering sleep mode due to bus low for period > t
f
The maximum t
This device internally provides a hold time of at least 100ns for the SDA signal (referred to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
C
The AIN
Accuracy specification valid for V
SCL
b
– total capacitance of one bus line in pF.
must meet the minimum clock low time plus the rise/fall times.
GERR
A
spec is only valid when this equation is satisfied: (V
= -20°C to +70°C.)
HD:DAT
has only to be met if the device does not stretch the LOW period (t
SYMBOL
t
t
SS
t
t
t
t
HD:STA
HD:DAT
SU:DAT
SU:STO
C
SU:STA
t
SLEEP
t
C
t
SS
f
HIGH
.
LOW
t
C
SCL
BUF
t
t
BUS
SP
BIN
R
F
- SNS ≥ ±2.5mV, below which offset error is dominant.
B
V
(Note 3)
(Note 4)
(Note 6, 7)
(Note 6)
(Note 8)
(Note 9)
(Note 5)
PIN
= 0.4V
3 of 17
CONDITIONS
il
AINx
.) AND ( SDA < V
+ 2V
OUT
)  (11.6V - (T
20 + 0.1C
20 + 0.1C
il
MIN
100
1.5
1.3
0.6
1.3
0.6
0.6
0.6
).
0
0
0
LOW
A
- 25C)10mV/C). See Figure 1.
) of the SCL signal.
B
B
TYP
SLEEP
MAX
400
300
300
400
2.2
0.9
50
50
60
.
UNITS
KHz
pF
pF
pF
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
S