CP2402-GM Silicon Laboratories Inc, CP2402-GM Datasheet - Page 58

• Manufacturer Part Number: CP2402-GM
• Description: IC LCD DRIVER 32QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2402-GM

• Package / Case: 32-QFN
• Display Type: LCD
• Configuration: 64 Segment
• Interface: SPI Serial
• Current - Supply: 620µA
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1863-5

CP2400/1/2/3
9.8.
The MSCN and MSCF registers provide additional ways of saving power by disabling unnecessary functionality.
SFR Definition 9.4. MSCN: Master Control Register
Address = 0xA0
58
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
CLKOVR
Disabling Secondary Device Functions
RTCBYP
ULPRST
ADRINV
SRAMD
RTCOD
CLEAR
LCDEN
Name
RTCBYP
R/W
7
0
SmaRTClock Oscillator Bypass.
When set to 1, the SmaRTClock oscillator clock is bypassed and the CLK pin is used to drive
the low frequency clock used for ULP operations.
ULP Status Clear.
Writing 1 to this register clears all bits in the ULP status register (ULPST).
SRAM Address Invert.
When set to 1, the least significant byte of the SRAM target address is inverted. This allows
the SRAM to be accessed in reverse sequential order using a single block read or write. For
example, a block read from addresses 0x0400 to 0x04FF will return data from RAM locations
0x04FF to 0x0400.
SmaRTClock Oscillator Output Disable.
When set to 1, the SmaRTClock oscillator output is gated off, and does not drive the low
frequency clock used for ULP operations.
SRAM Disable.
0: The SRAM is enabled.
1: The SRAM is disabled.
System Clock Override.
0: The CLKSL register determines the system clock.
1: The system clock is the CMOS clock input through the CLK pin.
ULP Memory Reset.
Writing 1 to this bit clears all values in the ULP Memory to 0x00. This bit can be used to
quickly set all ULP Port Mask bits to logic 0.
LCD Enable.
0: LCD Functionality is disabled.
1: LCD Functionality is enabled.
CLEAR
R/W
6
0
ADRINV
R/W
5
0
RTCOD
R/W
Rev. 1.0
4
0
SRAMD
Function
R/W
3
0
CLKOVR
R/W
2
0
ULPRST
R/W
1
0
LCDEN
R/W
0
0