TC7136CKW713 Microchip Technology, TC7136CKW713 Datasheet - Page 10

IC ADC 3 1/2DGT LOW PWR 44-MQFP

TC7136CKW713

Manufacturer Part Number
TC7136CKW713
Description
IC ADC 3 1/2DGT LOW PWR 44-MQFP
Manufacturer
Microchip Technology
Datasheet

Specifications of TC7136CKW713

Display Type
LCD
Configuration
7 Segment
Digits Or Characters
A/D 3.5 Digits
Current - Supply
70µA
Voltage - Supply
9V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-MQFP, 44-PQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Interface
-

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Part Number
Manufacturer
Quantity
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Part Number:
TC7136CKW713
Manufacturer:
Microchip Technology
Quantity:
10 000
TC7136/TC7136A
4.0
In addition to the basic integrate and de-integrate dual
slope cycles discussed above, the TC7136 and
TC7136A designs incorporate an "integrator output
zero cycle" and an "auto-zero cycle." These additional
cycles ensure the integrator starts at 0V (even after a
severe over range conversion) and that all offset volt-
age errors (buffer amplifier, integrator and comparator)
are removed from the conversion. A true digital zero
reading is assured without any external adjustments.
A complete conversion consists of four distinct phases:
1.
2.
3.
4.
4.1
This phase ensures the integrator output is at 0V
before the system zero phase is entered. This ensures
that true system offset voltages will be compensated
for, even after an over range conversion. The count for
this phase is a function of the number of counts
required by the de-integrate phase. The count lasts
from 11 to 140 counts for non over range conversions
and from 31 to 640 counts for over range conversions.
4.2
During the auto-zero phase, the differential input signal
is disconnected from the circuit by opening internal
analog gates. The internal nodes are shorted to analog
common (ground) to establish a zero input condition.
Additional analog gates close a feedback loop around
the integrator and comparator. This loop permits com-
parator offset voltage error compensation. The voltage
level established on C
voltages. The auto-zero phase residual is typically
10μV to 15μV.
The auto-zero duration is from 910 to 2900 counts for
non over range conversions and from 300 to 910
counts for over range conversions.
4.3
The auto-zero loop is entered and the internal differen-
tial inputs connect to V
input signal is integrated for a fixed time period. The
TC7136/A signal integration period is 1000 clock peri-
ods or counts. The externally set clock frequency is
divided by four before clocking the internal counters.
The integration time period is:
EQUATION 4-1:
DS21461C-page 10
Integrator output zero phase
Auto-zero phase
Signal integrate phase
Reference de-integrate phase
Where F
ANALOG SECTION
Integrator Output Zero Phase
Auto-Zero Phase
Signal Integration Phase
OSC
t
SI
=
= external clock frequency.
AZ
F
IN
OSC
compensates for device offset
4
+ and V
x 1000
IN
-. The differential
The differential input voltage must be within the device
Common mode range when the converter and mea-
sured system share the same power supply common
(ground). If the converter and measured system do not
share the same power supply common, V
tied to analog common.
Polarity is determined at the end of signal integrate
phase. The sign bit is a true polarity indication, in that
signals less than 1LSB are correctly determined. This
allows precision null detection, limited only by device
noise and auto-zero residual offsets.
4.4
The third phase is reference integrate or de-integrate.
V
V
ence capacitor. Circuitry within the chip ensures that
the capacitor will be connected with the correct polarity
to cause the integrator output to return to zero. The
time required for the output to return to zero is propor-
tional to the input signal and is between 0 and 2000
internal clock periods. The digital reading displayed is:
EQUATION 4-2:
FIGURE 4-1:
FIGURE 4-2:
DEINT
IN
IN
DENT
- is internally connected to analog common and
+ is connected across the previously charged refer-
INT
INT
AZ
AZ
ZI
ZI
Reference Integrate Phase
1000
1000
1000
CONVERSION TIMING
DURING NORMAL
OPERATION
CONVERSION TIMING
DURING OVER RANGE
OPERATION
1-2000
© 2005 Microchip Technology Inc.
=
2001-2090
----------------
V
V IN
REF
4000
4000
31-640
300-910
11-140
910-2900
IN
- should be

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