ADE7754AR Analog Devices Inc, ADE7754AR Datasheet - Page 37

• Manufacturer Part Number: ADE7754AR
• Description: IC ENERY METER 3PHASE 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of ADE7754AR

• Input Impedance: 370 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 7mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• For Use With: EVAL-ADE7754EBZ - BOARD EVALAUTION FOR ADE7754
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AD71049AR; AD71049AR

Measurement Mode Register (0Bh)
The configuration of the period and peak measurements made by the ADE7754 are defined by writing to the MMODE register.
Table XII summarizes the functionality of each bit in the MMODE register.
Bit
Location
0-1
2-3
4-6
7
Waveform Mode Register (0Ch)
The waveform sampling mode of the ADE7754 is defined by writing to the WAVMODE register. Table XIII summarizes the func-
tionality of each bit in the WAVMODE register.
Bit
Location
0-2
3-4
5
REV. 0
Bit
Mnemonic
PERDSEL
PEAKSEL
ZXSEL
Bit
Mnemonic
WAVSEL
DTRT
LVARSEL
Default
Value
0
0
7
Default
Value
0
0
0
Description
These bits are used to select the source of the measurement of the voltage line period.
Bit 1
0
0
1
1
selected line voltage is above the level defined in the PKVLVL register, the PKV flag in the
interrupt status register is set. If the selected current input is above the level defined in the
PKILVL register, the PKI flag in the interrupt status register is set.
Bit 3
0
0
1
1
These bits select the phases used for counting the number of zero crossing in the line active
and apparent accumulation modes as well as enabling these phases for the zero-crossing
timeout detection, zero crossing, period measurement, and SAG detection. Bits 4, 5, and 6
select Phase A, Phase B, and Phase C, respectively.
Reserved.
Description
These bits are used to select the source of the waveform sample.
Bit 2
0
0
0
0
1
1
1
These bits are used to select the waveform sampling update rate.
Bit 4
0
0
1
1
This bit is used to enable the accumulation of the line VAR energy into the LAENERGY register
and of the line active energy into the LVAENERGY register.
These bits select the line voltage and current phase used for the PEAK detection. If the
Table XIII. WAVMODE Register
Table XII. MMODE Register
0
1
0
1
0
1
0
1
Bit 1
0
0
1
1
0
0
1
Bit 3
0
1
0
1
Bit 0
Bit 2
–37–
Source
Phase A
Phase B
Phase C
Reserved
Source
Phase A
Phase B
Phase C
Reserved
Bit 0
0
1
0
1
0
1
0 or 1
Update Rate
26.0 kSPS (CLKIN/3/128)
13.0 kSPS (CLKIN/3/256)
6.5 kSPS (CLKIN/3/512)
3.3 kSPS (CLKIN/3/1024)
Source
Voltage Phase A
Voltage Phase B
Voltage Phase C
Current Phase A
Current Phase B
Current Phase C
Reserved
ADE7754