LTC4214-2CMS#TR Linear Technology, LTC4214-2CMS#TR Datasheet - Page 29

• Manufacturer Part Number: LTC4214-2CMS#TR
• Description: IC CONTROLLER HOTSWAP NEG 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4214-2CMS#TR

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 6 V ~ 16 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Soft-Start
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 1.6V in about 220 s at GATE
start-up, as shown in Figure 17a. If a soft-start capacitor,
C
modified from a linear ramp to an RC response (Equa-
tion 6), as shown in Figure 17b. This feature allows load
current to slowly ramp-up at GATE start-up. Soft-start is
initiated at time point 3 by a TIMER transition from V
to V
the V
the SS pin is below 0.2V, the analog current limit amplifier
holds GATE low. Above 0.2V, GATE is released and 50 A
ramps up the compensation network and GATE capaci-
tance at time point 4. Meanwhile, the SS pin voltage
continues to ramp up. When GATE reaches the MOSFET’s
threshold, the MOSFET begins to conduct. Due to the
MOSFET’s high g
SS
, is connected to this SS pin, the soft-start response is
TMRL
OVHI
(time points 1 to 2) or by the OV pin falling below
– V
OVHST
PWRGD
TIMER
SENSE
DRAIN
GATE
20 • (V
m
SS
, the MOSFET current quickly reaches
threshold after an OV condition. When
U
V
END OF INTIAL TIMING CYCLE
12 34 567
GS(th)
ACL
(17a) Without External C
V
V
TMRH
TMRL
+ V
50 A
20 • V
U
OS
)
40 A + 8 • I
20 • (V
OS
Figure 17. Soft-Start Timing (All Waveforms are Referenced to V
7a
CB
+ V
W
DRN
OS
)
8 9
50 A
V
V
V
10
ACL
CB
DRNCL
SS
V
5 A
DRNL
11
U
V
IN
– V
TMRH
GATEH
PWRGD
TIMER
SENSE
DRAIN
GATE
SS
the soft-start control value of V
point 6, the GATE voltage is controlled by the current limit
amplifier. The soft-start control voltage reaches the circuit
breaker voltage, V
TIMER activates. As the load capacitor nears full charge,
load current begins to decline below V
limit loop shuts off and GATE releases at time point 8. At
time point 9, the SENSE voltage falls below V
TIMER deactivates.
Large values of C
time out as V
the circuit breaker delay. The load capacitor is unable to
achieve full charge in one GATE start-up cycle. A more
serious side effect of large C
be exceeded during soft-start into a low impedance load.
A soft-start voltage below V
breaker TIMER.
V
END OF INTIAL TIMING CYCLE
12 3 4 5 6
GS(th)
V
V
TMRH
TMRL
(17b) With External C
50 A
20 • V
20 • (V
40 A + 8 • I
LTC4214-1/LTC4214-2
OS
ACL
ACL
7
(t) may exceed the V
+ V
CB
SS
OS
DRN
, at time point 7 and the circuit breaker
can cause premature circuit breaker
)
8 9
20 • (V
50 A
EE
V
V
V
SS
10
ACL
CB
DRNCL
)
V
5 A
SS
DRNL
CB
4214 F17
CB
11
V
+ V
values is SOA duration may
IN
ACL
will not activate the circuit
– V
OS
)
(t) (Equation 7). At time
GATEH
CB
ACL
potential during
(t). The current
29
CB
421412f
and