LT4256-3IGN Linear Technology, LT4256-3IGN Datasheet - Page 11

• Manufacturer Part Number: LT4256-3IGN
• Description: IC CTRLR HOTSWP HV DETECT 16SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LT4256-3IGN

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 10.8 V ~ 80 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
To reduce inrush current, increase C1 or decrease load
capacitance. If the voltage across the current sense resis-
tor R5 reaches V
ited by the internal current limit circuitry. The voltage on
GATE is adjusted to maintain a constant voltage across the
sense resistor and TIMER begins to charge.
When the FB voltage goes above the low-to-high V
threshold, PWRGD goes high.
Undervoltage and Overvoltage Detection
The LT4256-3 uses UV and OV to monitor the V
to determine when it is safe to turn on the load and allow
the user the greatest flexibility for setting the operational
thresholds. UV and OV are internally connected to an
analog window comparator. Any time that UV goes below
3.6V or OV goes above 4V, GATE will be pulled low until the
UV/OV voltages return to the normal operation voltage
window (4V and 3.6V, respectively).
The UV threshold should never be set below the internal
UVLO threshold (9.8V typically) because the benefit of the
UV’s hysteresis will be lost, making the LT4256-3 more
susceptible to noise (V
is at its 3.6V threshold). UV is filtered with C3 to prevent
OFF SIGNAL
FROM MPU
SENSETRIP
U
CC
must be at least 9.8V when UV
U
, the inrush current will be lim-
GND
Figure 7. How to Use a Logic Signal to Control the LT4256-3 Turn On/Off
V
48V
Q2
VN2222
CC
0.01µF
(SHORT PIN)
W
C3
R1
64.9k
R2
4.02k
R3
4.02k
CC
U
C2
33nF
D2
SMAT70A
voltage
1
2
4
9
UV
OV
OPEN
TIMER
V
FB
CC
LT4256-3
16
0.010Ω
GND
R5
8
SENSE
PWRGD
RETRY
noise spikes and capacitively coupled glitches from shut-
ting down the LT4256-3 output erroneously.
To calculate UV and OV thresholds, use the following
equations:
where V
threshold voltages when V
Figure 7 shows how the LT4256-3 is commanded to shut
off with a logic signal. This is accomplished by pulling the
gate of the open-drain MOSFET, Q2, (tied to UV) high.
GATE
V
15
OUT
FB
R
R
20
V
V
THUVHL
THOVHL
1
3
13
12
10
7
5
k
=
=
Ω ≤
IRF540
(
THULH
UV = 36V
OV = 73V
PWRGD = 40V
Q1
R
V
THOVLH
R7
100Ω
2
R6
10Ω
R
C1
10nF
+
R
=
=
1
4
1
+
R
3 6
3 6
and V
+
3
D1
CMPZ5241BS
11V
R
.
.
)
R
2
⎛
⎜
⎝
V
V
–
2
V
⎛
⎜
⎝
⎛
⎜
⎝
1
+
THUVLH
1
1
THOVLH
+
+
4
R
V
3
R
R
R9
4.02k
R8
36.5k
2
1
≤
R
CC
R
+
4256 F07
+
3
1
–
200
R
are the desired UV and OV
R
is rising (L – H).
1
2
3
⎞
⎟
⎠
R4
51k
⎞
⎟
⎠
+
⎞
⎟
⎠
k
;
Ω
C
L
V
48V
4A
OUT
LT4256-3
11
42563fa
( )
( )
2
2
( )
( )
a
b
3
4