LTC1646CGN#TRPBF Linear Technology, LTC1646CGN#TRPBF Datasheet - Page 10

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LTC1646CGN#TRPBF

Manufacturer Part Number
LTC1646CGN#TRPBF
Description
IC CNTRLR HOTSWAP PCIDUAL 16SSOP
Manufacturer
Linear Technology
Type
Hot-Swap Controllerr
Datasheet

Specifications of LTC1646CGN#TRPBF

Applications
CompactPCI™
Internal Switch(s)
No
Voltage - Supply
3.3V, 5V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-SSOP (0.150", 3.90mm Width)
Linear Misc Type
Positive Low Voltage
Family Name
LTC1646
Package Type
SSOP N
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
7V
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Product Depth (mm)
3.99mm
Product Height (mm)
1.5mm
Mounting
Surface Mount
Pin Count
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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LTC1646
APPLICATIO S I FOR ATIO
4. Programmable foldback current limit: a programmable
5. Dual-level, programmable 5V and 3.3V circuit breakers:
6. 15V high side drive for external 3.3V and 5V N-channel
7. PWRGD output: monitors the voltage status of the
8. PCI_RST# combined on-chip with HEALTHY# to create
9. Precharge output: on-chip reference and amplifier pro-
10. Space saving 16-pin SSOP package.
PCI Power Requirements
CPCI systems may require up to four power rails: 5V, 3.3V,
12V and –12V. The LTC1646 is designed for CPCI applica-
tions which only use the 5V and/or 3.3V supplies. The
tolerance of the supplies as measured at the components
on the plug-in card is summarized in Table 1.
Table 1. PCI Power Supply Requirements
SUPPLY
5V
3.3V
Power-Up Sequence
The LTC1646 is specifically designed for hot swapping
CPCI boards. The typical application is shown in Figure 1.
10
analog current limit with a value that depends on the
output voltage. If the output is shorted to ground, the
current limit drops to keep power dissipation and
supply glitches to a minimum.
this feature is enabled when the TIMER pin voltage
exceeds 1.25V. If either supply exceeds current limit
for more than 21µs, the circuit breaker will trip, the
supplies will be turned off, and the FAULT pin is pulled
low. In the event that either supply exceeds three times
the set current limit, all supplies will be turned off and
the FAULT pin is pin is pulled low without delay.
MOSFETs.
supply voltages.
LOCAL_PCI_RST# output. If HEALTHY# deasserts,
LOCAL_PCI_RST# is asserted independent of
PCI_RST#.
vide 1V for biasing bus I/O connector pins during CPCI
card insertion and extraction.
U
TOLERANCE
3.3V ±0.3V
5V ±5%
U
W
CAPACITIVE LOAD
< 3000µF
< 3000µF
U
The main 3.3V and 5V inputs to the LTC1646 come from
the medium length power pins. The long 3.3V, 5V connec-
tor pins are shorted to the medium length 5V and 3.3V
connector pins on the CPCI plug-in card and provide early
power for the LTC1646’s precharge circuitry, the V(I/O)
pull-up resistors and the PCI bridge chip. The BD_SEL#
signal is connected to the OFF/ON pin while the PWRGD
pin is connected to the HEALTHY# signal. The HEALTHY#
signal is combined with the PCI_RST# signal on-chip to
generate the LOCAL_PCI_RST# signal which is available
at the RESETOUT pin.
The power supplies are controlled by placing external
N-channel pass transistors in the 3.3V and 5V power
paths.
Resistors R1 and R2 provide current fault detection and
R5 and C1 provide current control loop compensation.
Resistors R3 and R4 prevent high frequency oscillations
in Q1 and Q2.
When the CPCI card is inserted, the long 5V and 3.3V
connector pins and GND pins make contact first. The
LTC1646’s precharge circuit biases the bus I/O pins to 1V
during this stage of the insertion (Figure 2). The 5V and
3.3V medium length pins make contact during the next
stage of insertion, but the slot power is disabled as long
as the OFF/ON pin is pulled high by the 1.2k pull-up
resistor to V(I/O). During the final stage of board insertion,
the BD_SEL# short connector pin makes contact and the
OFF/ON pin can be pulled low. This enables the pass
transistors to turn on and a 5µA current source is con-
nected to the TIMER pin.
The current in each pass transistor increases until it
reaches the current limit for each supply. The 5V and 3.3V
supplies are then allowed to power up based on one of the
following power-up rates:
whichever is slower.
Current limit faults are ignored while the TIMER pin
voltage is ramping up and is less than 1.25V. Once both
supply voltages are within tolerance, HEALTHY# will pull
low and LOCAL_PCI_RST# is free to follow PCI_RST#.
dV
dt
=
13
C
µ
1
A
,
or
=
C
LOAD VOUT
I
LIMIT V
(
5
(
5
)
)
,
or
=
C
LOAD VOUT
I
LIMIT V
(
3
(
3
)
)
1646fa
(1)

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