LTC4215IUFD-1#PBF Linear Technology, LTC4215IUFD-1#PBF Datasheet - Page 12

• Manufacturer Part Number: LTC4215IUFD-1#PBF
• Description: IC CTLR HOT SWAP 24-QFN
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4215IUFD-1#PBF

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 2.9 V ~ 15 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC4215/LTC4215-2
APPLICATIONS INFORMATION
A typical LTC4215 application is in a high availability system
in which a positive voltage supply is distributed to power
individual cards. The device measures card voltages and
currents and records past and present fault conditions.
The system queries each LTC4215 over the I
and reads status and measurement information.
A basic LTC4215 application circuit is shown in Figure 1.
The following sections cover turn-on, turn-off and various
faults that the LTC4215 detects and acts upon. External
component selection is discussed in detail in the Design
Example section.
Turn-On Sequence
The power supply on a board is controlled by using an
external N-channel pass transistor (Q1) placed in the power
path. Note that resistor R
sistors R1, R2 and R3 defi ne undervoltage and overvoltage
levels. R5 prevents high frequency oscillations in Q1 and
R6 and C1 form an optional network that may be used to
provide an output dV/dt limited start-up.
Several conditions must be present before the external
MOSFET turns on. First the external supply, V
exceed its 2.84V undervoltage lockout level. Next the
internally generated supply, INTV
undervoltage threshold. This generates a 60μs to 120μs
12
ALERT
GND
SDA
SCL
12V
BACKPLANE
PLUG-IN
CARD
S
provides current detection. Re-
0.1μF
CC
Z1
P6KE16A
C
F
, must cross its 2.64V
3.4K
1%
R3
R2
1.18k
1%
R1
34.8k
1%
2
C periodically
Figure 1. Typical Application
DD
OV
ON
SDAI
SDA0
SCL
ALERT
, must
C
0.68μF
TIMER
UV V
TIMER INTV
DD
SENSE
power-on-reset pulse. During reset the fault registers are
cleared and the control registers are set or cleared as
described in the register section.
After a power-on-reset pulse, the LTC4215 goes through
the following turn-on sequence. First the UV and OV pins
indicate that input power is within the acceptable range,
which is indicated by bits C0-C1 in Table 4. Second, the EN
pin is externally pulled low. Finally, all of these conditions
must be satisfi ed for the duration of 100ms to ensure that
any contact bounce during insertion has ended.
When these initial conditions are satisfi ed, the ON pin is
checked and it’s state written to bit A3 in Table 2. If it is
high, the external MOSFET is turned on. If the ON pin is
low, the external MOSFET is turned on when the ON pin is
brought high or if a serial bus turn-on command is sent
by setting bit A3.
The MOSFET is turned on by charging up the GATE with
a 20μA current source. When the GATE voltage reaches
the MOSFET threshold voltage, the MOSFET begins to
turn on and the SOURCE voltage then follows the GATE
voltage as it increases.
When the MOSFET is turning on, it ramps inrush current
up linearly at a dI/dt rate selected by capacitor C
the inrush current reaches the limit set by the FB pin, the
0.005Ω
+
RS
LTC4215UFD
CC
SENSE
C3
0.1μF
ADR0
10Ω
R5
–
FDC653N
GATE
Q1
ADR1 ADR2
6.8nF
15k
R6
C1
SOURCE
GND
ADIN
GPIO
EN
SS
FB
4215 F01
R7
30.1k
1%
R8
3.57k
1%
C
7.5nF
SS
R4
100k
+
C
330μF
L
V
12V
OUT
SS
. Once
4215fe