MAX3946ETG+ Maxim Integrated Products, MAX3946ETG+ Datasheet - Page 16

• Manufacturer Part Number: MAX3946ETG+
• Description: IC LASER DVR SFP 11.3GBPS 24TQFN
• Manufacturer: Maxim Integrated Products
• Type: Laser Diode Driverr

Specifications of MAX3946ETG+

• Data Rate: 11.3Gbps
• Number Of Channels: 1
• Voltage - Supply: 2.85 V ~ 3.63 V
• Current - Supply: 68mA
• Current - Modulation: 80mA
• Current - Bias: 80mA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 12-WFQFN, Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3. Digital Communication Word Structure
Table 4. Register Descriptions and Addresses
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
The device implements a proprietary 3-wire digital inter-
face. An external controller generates the clock. The
3-wire interface consists of an SDA bidirectional data
line, an SCL clock signal input, and a CSEL chip-select
input (active high). The external master initiates a data
transfer by asserting the CSEL pin. The master starts to
generate a clock signal after the CSEL pin has been set
to a logic-high. All data transfers are most significant bit
(MSB) first.
Each operation consists of 16-bit transfers (15-bit
address/data, 1-bit RWN). The bus master generates 16
clock cycles to SCL. All operations transfer 8 bits to the
device. The RWN bit determines if the cycle is read or
write. See Table 3.
The device contains 13 registers available for program-
ming. Table 4 shows the registers and addresses.
The master generates 16 total clock cycles at SCL. The
master outputs a total of 16 bits (MSB first) to the SDA
line at the falling edge of the clock. The master closes
the transmission by setting CSEL to 0. Figure 5 shows
the interface timing.
16
15
_____________________________________________________________________________________
ADDRESS
H0x0C
H0x0D
H0x0A
H0x0B
H0x0E
H0x05
H0x06
H0x07
H0x08
H0x09
H0x0F
H0x10
H0x11
14
13
Register Address
12
SET_PWCTRL
MODECTRL
SET_IMOD
SET_TXEQ
SET_IBIAS
IMODMAX
SET_TXDE
IBIASMAX
TXSTAT1
TXSTAT2
MODINC
BIASINC
TXCTRL
NAME
11
Write Mode (RWN = 0)
Register Addresses
3-Wire Interface
10
Transmitter Control Register
Transmitter Status Register 1
Transmitter Status Register 2
Bias Current Setting Register
Modulation Current Setting Register
Maximum Modulation Current Setting Register
Maximum Bias Current Setting Register
Modulation Current Increment Setting Register
Bias Current Increment Setting Register
Mode Control Register
Pulse-Width Control Register
Deemphasis Control Register
Equalization Control Register
Protocol
9
RWN
8
BIT
The master generates 16 total clock cycles at SCL. The
master outputs a total of 8 bits (MSB first) to the SDA line
at the falling edge of the clock. The SDA line is released
after the RWN bit has been transmitted. The slave out-
puts 8 bits of data (MSB first) at the rising edge of the
clock. The master closes the transmission by setting
CSEL to 0. Figure 5 shows the interface timing.
Normal mode allows read-only instruction for all regis-
ters except MODINC and BIASINC. The MODINC and
BIASINC registers can be updated during normal mode.
Doing so speeds up the laser control update through the
3-wire interface by a factor of two. The normal mode is
the default mode.
Setup mode allows the master to write unrestricted data
into any register except the status (TXSTAT1, TXSTAT2)
registers. To enter the setup mode, the MODECTRL
register (address = H0x0E) must be set to H0x12. After
the MODECTRL register has been set to H0x12, the
next operation is unrestricted. The setup mode is auto-
matically exited after the next operation is finished. This
sequence must be repeated if further unrestricted set-
tings are necessary.
7
6
FUNCTION
Data that is written or read
5
4
3
Read Mode (RWN = 1)
2
Mode Control
1
0