LTC1163CS8#PBF Linear Technology, LTC1163CS8#PBF Datasheet - Page 5

• Manufacturer Part Number: LTC1163CS8#PBF
• Description: IC MOSFET DVR HI-SIDE TRPL 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC1163CS8#PBF

• Configuration: High-Side
• Input Type: Non-Inverting
• Delay Time: 130µs
• Number Of Configurations: 3
• Number Of Outputs: 3
• Voltage - Supply: 1.8 V ~ 6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Peak: -
• High Side Voltage - Max (bootstrap): -

OPERATIO
APPLICATIO S I FOR ATIO
BLOCK DIAGRA
Gate Charge Pump
Gate drive for the power MOSFET is produced by an
internal charge pump circuit which generates a gate volt-
age substantially higher than the power supply voltage.
The charge pump capacitors are included on chip and
therefore no external components are required to generate
gate drive.
Logic-Level MOSFET Switches
The LTC1163/LTC1165 are designed to operate with
logic-level N-channel MOSFET switches. Although there
is some variation among manufacturers, logic-level
MOSFET switches are typically rated with V
a maximum continuous V
maximum V
and there is generally little price differential. Logic-level
MOSFETs are frequently designated by an “L” and are
usually available in surface mount packaging. Some
logic-level MOSFETs are rated with V
can be used in applications which require operation over
the entire 1.8V to 6V range.
Powering Large Capacitive Loads
Electrical subsystems in portable battery-powered equip-
ment are typically bypassed with large filter capacitors to
reduce supply transients and supply induced glitching. If
not properly powered however, these capacitors may
themselves become the source of supply glitching.
DS
ratings are similar to standard MOSFETs
U
U
GS
U
W
INPUT
rating of 10V. R
(One Channel)
W
GS
LTC1165
LTC1163
up to 15V and
GS
DS(ON)
= 4V with
U
OSCILLATOR
GENERATOR
FREQUENCY
and
HIGH
BIAS
Controlled Gate Rise and Fall Times
When the input is switched ON and OFF, the gate is
charged by the internal charge pump and discharged in a
controlled manner. The charge and discharge rates have
been set to minimize RFI and EMI emissions.
For example, if a 100 F capacitor is powered through a
switch with a slew rate of 0.1V/ s, the current during start-
up is:
Obviously, this is too much current for the regulator (or
output capacitor) to supply and the output will glitch by as
much as a few volts.
The startup current can be substantially reduced by limit-
ing the slew rate at the gate of an N-channel as shown in
Figure 1. The gate drive output of the LTC1163/LTC1165
is passed through a simple RC network, R1 and C1, which
substantially slows the slew rate of the MOSFET gate to
approximately 1.5
operating as a source follower, the slew rate at the source
is essentially the same as that at the gate, reducing the
startup current to approximately 15mA which is easily
I
START
DISCHARGE
CHARGE
LOGIC
PUMP
GATE
= C( V/ t)
= (100 10
= 10A
14V
LTC1163/65 • BD
– 6
10
GATE
)(1 10
LTC1163/LTC1165
– 4
V/ s. Since the MOSFET is
5
)
5