IR21141SSPBF International Rectifier, IR21141SSPBF Datasheet - Page 13

• Manufacturer Part Number: IR21141SSPBF
• Description: IC DRVR HALF BRIDGE 600V 24-SSOP
• Manufacturer: International Rectifier

Specifications of IR21141SSPBF

• Configuration: Half Bridge
• Input Type: Non-Inverting
• Delay Time: 440ns
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 600V
• Voltage - Supply: 11.5 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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The external sensing diode should have breakdown
voltage greater than 600 V (IR2114) or 1200 V (IR2214),
low stray capacitance and low recovery current (in order
to minimize noise coupling and switching delays). In
series an external decoupling 1K
order to limit the current flowing in and out of DSH and
DSL pins because of switching noise coupled through
the external de-saturation sensing diode. The diode is
biased by an internal pull-up resistor R
V
the DSH or DSL pin increases too. Being internally
biased to the local supply, the DSH/DSL voltage is
automatically clamped. When DSH/DSL exceeds the
V
The comparator’s output is filtered in order to avoid false
desaturation detection by externally induced noise;
pulses shorter than t
detecting a false desaturation event during IGBT turn on,
the desaturation circuit is disabled by a blanking signal
(T
estimated maximum IGBT turn on time and must be not
exceeded by proper gate resistance sizing. When the
IGBT is not completely saturated after T
is detected and the driver will turn off.
Eligible desaturation signals initiate the SSD sequence.
While in SSD, the driver’s output goes to a high
impedance state and the SSD pull-down is activated to
CC
DESAT+
BL
/I
, see blanking block in Fig. 13). This time is the
DS-
threshold, the comparator triggers (see Fig. 13).
or V
BS
/I
DS-
). When V
(external hard
FAULT/SD
shutdown)
SY_FLT
(external
DS
FLTCLR
hold)
are filtered out. To avoid
CE
increases, the voltage at
resistor is required in
Figure 13: High and Low Side Output Stage
Figure 14: Fault Management Diagram
internal
HOLD
BL
DSH/L
, desaturation
(equal to
(hard shutdown)
internal FAULT
13
turn off the IGBT through the SSDH/SSDL pin. The
SY_FLT output pin (active low, see Fig. 14) reports the
gate driver status during the SSD sequence (t
the SSD has finished, SY_FLT releases, and the gate
driver generates a FAULT signal (see the FAULT/SD
section) by activating the FAULT/SD pin. This generates
a hard shutdown for both the high and low output stages
(HO=LO=low). Each driver is latched low until the fault is
cleared (see FLT_CLR).
Figure 14 shows the fault management circuit. In this
diagram DesatHS and DesatLS are two internal signals
that come from the output stages (see Fig. 13).
It must be noted that while in SSD, both the
undervoltage fault and external SD are masked until the
end of SSD. Desaturation protection is working
independently by the other control pin and it is disabled
only when the output status is off.
For the purpose of sensing the power transistor
desaturation, the collector voltage is monitored (an
external high voltage diode is connected between the
IGBT’s collector and the IC’s DSH or DSL pin). The
diode is normally biased by an internal pull up resistor
connected to the local supply line (V
transistor is “on” the diode is conducting and the amount
Q
Q
SET
CLR
R
S
IR2114/IR2214SSPbF
DesatHS
DesatLS
UVCC
© 2009 International Rectifier
B
or V
CC
). When the
SS
). Once