LTC1472CS#TRPBF Linear Technology, LTC1472CS#TRPBF Datasheet - Page 11

• Manufacturer Part Number: LTC1472CS#TRPBF
• Description: IC SWITCHNG MATRIX PCMCIA 16SOIC
• Manufacturer: Linear Technology
• Type: PCMCIA/Cardbus Switchr

Specifications of LTC1472CS#TRPBF

• Number Of Outputs: 1
• Rds (on): 180 mOhm
• Internal Switch(s): Yes
• Current Limit: 1A
• Voltage - Input: 3.3V, 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS
Output Capacitors
The V
400µs rise time. Therefore, capacitors as large as 150µF
can be driven without producing voltage spikes on the
5V
mance Characteristics). The V
0.1µF to 1µF capacitor for noise reduction and smoothing.
The VPP
for noise reduction. The VPP
least equal to the VPP
transitions between output voltages without creating spikes
on the system power supply lines.
Supply Sequencing
Because the 5V supply is the source of power for both the
V
power supplies such that the 5V supply is powered before
or simultaneous to the application of 3.3V or 12V power.
It is interesting to note however, that all of the switches in
the LTC1472 are NMOS transistors which require charge
pumps to generate gate voltages higher than the supply
rails for full enhancement. Because the gate voltages start
CC
IN
and VPP switch control logic, it is best to sequence the
or 3V
CC(OUT)
OUT
IN
pin should have a 0.01µF to 0.1µF capacitor
pin is designed to ramp on slowly, typically
supply pins (see graphs in Typical Perfor-
U
OUT
INFORMATION
U
capacitors to ensure smooth
IN
CC(OUT)
capacitors should be at
W
pin should have a
U
a 0V when the supplies are first activated, the switches
always start in the off state and do not produce glitches at
the output when powered.
Some PCMCIA switch matrix products employ PMOS
switches for 12V VPP control and great care must be taken
to ensure that the 5V control logic is powered before the
12V supply is turned on. If this sequence is not followed,
the PMOS VPP switch gate may start at ground potential
and the VPP output may be inadvertently forced to 12V.
Although, not advisable, it is possible to power the 12V
VPP
power. Only about 50µA flows to the VPP
these conditions.
If the 5V supply must be turned off, it is important to
program all switches to the Hi-Z or 0V state at least 100µs
before the 5V power is removed to ensure that all NMOS
switch gates are fully discharged to 0V.
Whenever possible however, it is best to leave the 5V
V
current drops to < 1µA with all the switches turned off and
therefore no 5V power is consumed in the standby mode.
DD
IN
pins continuously powered. The LTC1472 quiescent
supply pin of the LTC1472 prior to application of 5V
LTC1472
OUT
pin under
11
IN
1472fa
and