MAX5040EUB+ Maxim Integrated Products, MAX5040EUB+ Datasheet - Page 7

• Manufacturer Part Number: MAX5040EUB+
• Description: IC CNTRLR VOLT TRACK 10-UMAX
• Manufacturer: Maxim Integrated Products

Specifications of MAX5040EUB+

• Applications: Processor
• Current - Supply: 1.3mA
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Scope shots are of the MAX5040 EV kit. Figures 1
through 8 demonstrate system performance of the
MAX5040 under various power-up, power-down, and
fault conditions. In some cases (described in detail
below), startup or shutdown of the I/O and CORE sup-
plies were purposely delayed with respect to each
other to simulate possible system operating conditions.
In Figure 1 (with MAX5040), V
the I/O supply comes up before the CORE supply. As
soon as V
goes to V
er. When V
V
supplies. Although the CORE PWM supply turns on 5ms
after the I/O PWM supply, both supply voltages come up
together because NDRV is held at V
plies together through the N-channel FET. The I/O supply
supports both the I/O line and the CORE line. Once
V
2.8V to regulate V
the CORE supply comes up, NDRV goes to GND, and
POK goes high. On power-down, when V
enough to bring V
falls, turning the I/O and CORE supplies off. Simultane-
ously, POK falls, indicating power-down to the proces-
sor. When the I/O voltage drops below the CORE
voltage, NDRV goes to V
the supplies together. NDRV remains at V
falls below 2.5V and then it returns to GND.
In Figure 2 (without MAX5040), V
and the CORE and I/O supplies are turned on when
V
the CORE voltage. There is a 3.3V difference between
the I/O and CORE supplies for about 4ms before the
CORE supply finally comes up. When V
down, I/O remains high for about 10ms after CORE
reaches GND.
In Figure 3 (with MAX5040), V
the CORE supply comes up before the I/O supply. As
soon as V
goes to V
er. When V
V
supplies. Although the I/O PWM supply turns on 8ms
after the CORE PWM supply, both supply voltages come
up together because NDRV is held at V
supplies together through the N-channel FET. The CORE
supply supports both the CORE line and the I/O line until
the I/O supply comes up. At around 23ms, the I/O supply
UVCC
CORE
CC
UVCC
exceeds 2.5V. The I/O voltage comes up before
), SDO goes high enabling the I/O and CORE
), SDO goes high, enabling the I/O and CORE
rises close to its set point, NDRV falls to around
CC
CC
CC
CC
CC
CC
, shorting the I/O and CORE supplies togeth-
shorting the I/O and CORE supplies togeth-
rises above 2.5V (at about 7.5ms), NDRV
rises above 2.5V (at about 7.5ms) NDRV
rises above 4.5V (bringing V
rises above 4.5V (bringing V
CORE
UVLO
_______________________________________________________________________________________
Performance During
at its set point. At around 22ms,
below V
CC
Typical Operation
(at around 36ms), shorting
CC
CC
UVCC
ramps up slowly and
ramps up slowly and
CC
CC
, SDO immediately
, shorting the sup-
ramps up slowly
Voltage-Tracking Controllers for
CC
CC
, shorting the
CC
UVLO
UVLO
CC
drops low
until V
powers
above
above
PowerPC, DSPs, and ASICs
CC
turns on, pulling the I/O voltage above the CORE volt-
age. At this point, the MAX5040 brings NDRV to GND
and POK goes high. On power-down, when V
low enough to bring V
ately falls, turning the I/O and CORE supplies off.
Simultaneously POK falls, indicating power-down to the
processor. When the CORE voltage drops below its reg-
ulation point, NDRV begins to regulate it (at around
30ms). When I/O falls below CORE, NDRV is pulled up to
V
In Figure 4 (without MAX5040), V
and the CORE voltage comes up before the I/O volt-
age. It takes about 8ms before the I/O supply finally
comes up above the CORE supply. When V
down, the supplies do not turn off together. CORE
remains high for around 14ms after I/O falls.
In Figure 5 (with MAX5040), the system power-up is
attempted with the CORE supply held in shutdown. As
soon as V
shorting the I/O and CORE supplies together. Next,
when V
V
supplies. Both supplies come up together because
NDRV is high. Note that the CORE supply is still off;
CORE is held up through the N-channel FET shunt.
Once V
lator holds V
around 2.8V. After 15ms of regulating CORE, the
MAX5040 latches a fault. SDO goes low, NDRV goes to
V
remains low throughout because a valid operating state
was not achieved.
In Figure 6 (with MAX5040), V
UVLO from low to high controls system startup. While
UVLO is low and the V
the supplies to be shorted together. When UVLO goes
high, SDO also goes high, turning on the CORE and I/O
supplies (at around 3ms). In this example, the I/O sup-
ply comes up before the CORE supply. The MAX5040
regulates CORE by driving NDRV to about 2.8V until the
CORE supply comes up (at around 7ms), then NDRV
falls to GND and POK goes high. When UVLO is driven
low, SDO goes low, disabling the CORE and I/O sup-
plies. NDRV goes to V
down together.
In Figure 7 (with MAX5040), V
UVLO from low to high controls system startup. While
UVLO is low and the V
the supplies together while they are both off. When
UVLO does go high, SDO also goes high, turning on
the CORE and I/O supplies (at around 8ms). In this
example, the CORE supply comes up before the I/O
CC
UVCC
CC
, and both supplies power down together. POK
to short the two supplies together.
), SDO goes high, enabling the I/O and CORE
CORE
CC
CC
rises above 4.5V (bringing V
CORE
rises close to its set point, the linear regu-
rises above 2.5V, NDRV goes to V
to its set point by regulating NDRV to
UVLO
CC
CC
CC
is 5V, NDRV is high, shorting
is 5V, NDRV is high, causing
below V
and both supplies power
CC
CC
is set to 5V. Toggling
is set to 5V. Toggling
CC
UVCC
ramps up slowly
, SDO immedi-
UVLO
CC
CC
powers
above
drops
CC
7
,