IR3508ZMTRPBF International Rectifier, IR3508ZMTRPBF Datasheet
IR3508ZMTRPBF
Specifications of IR3508ZMTRPBF
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IR3508ZMTRPBF Summary of contents
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DESCRIPTION The IR3508Z Phase IC combined with any IR XPhase3 to implement a power solution for the latest high performance CPUs and ASICs. The “Control” IC provides overall system control and interfaces with any number of “Phase” ICs which each ...
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... ORDERING INFORMATION Part Number IR3508ZMTRPBF * IR3508ZMPBF * Samples only ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device, at these or any other conditions, beyond those indicated in the operational sections of the specifications are not implied. ...
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RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 8.0V ≤ V ≤ 28V, 4.75V ≤ CCL ≤ PHSIN ≤1.5MHz. ELECTRICAL CHARACTERISTICS The electrical characteristics table lists the parametric range guaranteed to be within the recommended operating conditions. Typical ...
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PARAMETER PWM Comparator PWM Ramp Slope Vin=12V EAIN Bias Current 0 ≤ EAIN ≤ 3V Minimum Pulse Width Note 1 Current Sense Amplifier CSIN+/- Bias Current CSIN+/- Bias Current Note 1 Mismatch Input Offset Voltage CSIN+ = CSIN- = DACIN. ...
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PARAMETER Body Brake Comparator Threshold Voltage with EAIN decreasing Threshold Voltage with EAIN increasing Hysteresis Propagation Delay OVP Comparator OVP Threshold Propagation Delay Synchronous Rectification Disable Comparator Threshold Voltage Negative Current Comparator Input Offset Voltage Propagation Delay Time Bootstrap Diode ...
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PIN DESCRIPTION PIN# PIN SYMBOL PIN DESCRIPTION 1 IOUT Output of the Current Sense Amplifier is connected to this pin through a 3k resistor. Voltage on this pin is equal to V(DACIN [V(CSIN+) – V(CSIN-)]. Connecting all IOUT ...
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SYSTEM THEORY OF OPERATION System Description The system consists of one control IC and a scalable array of phase converters, each requiring one phase IC. The control IC communicates with the phase ICs using three digital buses, i.e., CLOCK, PHSIN, ...
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Frequency and Phase Timing Control The oscillator is located in the Control IC and the system clock frequency is programmable from 250kHz to 9MHZ by an external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of ...
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PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; The ...
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Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR (R voltage across Ccs is proportional ...
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For proper current sharing the output of current sense amplifier should not exceed (VCCL-1.4V) under all operating condition. IR3508Z THEORY OF OPERATION ...
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A synchronous rectification disable comparator is used to detect the converter’s CSIN- pin voltage, which represents local converter output voltage. If the voltage is below 75% of VDAC and negative current is detected, GATEL is driven low, which disables synchronous ...
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Emulated Bootstrap Diode IR3508Z integrates a PFET to emulate the bootstrap diode. If two or more top MOSFETs are to be driven at higher switching frequency, an external bootstrap diode connected from VCCL pin to BOOST pin may be needed. ...
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DESIGN PROCEDURES - IR3508Z Inductor Current Sensing Capacitor C The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor R in parallel with the inductor are chosen to match the time constant of the ...
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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout; therefore, minimizing the noise coupled to the IC. • Dedicate at least one middle layer for a ground plane, which is ...
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PCB Metal and Component Placement • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part ...
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Solder Resist • The solder resist should be pulled away from the metal lead lands and center pad by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands ...
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Stencil Design • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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PACKAGE INFORMATION 20L MLPQ ( Body) – θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Visit us at www.irf.com for sales contact information. Page ...