LTC2922IF-2.5#PBF Linear Technology, LTC2922IF-2.5#PBF Datasheet - Page 12

• Manufacturer Part Number: LTC2922IF-2.5#PBF
• Description: IC 5 PWR SUPPLY MONITOR 20TSSOP
• Manufacturer: Linear Technology

Specifications of LTC2922IF-2.5#PBF

• Applications: Five Power Supply Monitor
• Voltage - Supply: 2.37 V ~ 2.63 V
• Current - Supply: 2mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

LTC2921/LTC2922 Series
APPLICATIO S I FOR ATIO
voltage specifications. On-resistance is a critical param-
eter when choosing power MOSFETs. The integrated
remote sense switches compensate for IR drops, but
minimizing V
resistive voltage divider for the monitors.
Setting the GATE Ramp Rate
Application of power to the loads is controlled by setting
the voltage ramping rate with an external capacitor on the
GATE pin. During Step 3 of the monitoring sequence, a
10 A pull-up ramps the GATE pin capacitance up to
V
to calculate the nominal GATE pin capacitance necessary
to achieve a given ramp rate, V/ t:
Alternatively, to calculate the GATE capacitor to achieve a
desired nominal ramp time, use Equation 6. The GATE
drive voltage (V
Electrical Characteristics table and Typical Performance
curves to choose an appropriate value to insert for V
When the GATE pin drives several FETs in parallel, the load
voltages ramp together at the same rate until the lowest
supply reaches its full value. The other supplies continue
to track until the next lowest supply reaches its full value,
and so on.
The GATE pin must not be forced above the level it reaches
when fully ramped. An internal clamp limits the GATE
voltage to 12.2V relative to ground.
Damp possible ramp-on oscillations by including a 10
resistor in series with each external N-channel gate, and as
necessary, a 0.1 F capacitor on each external N-channel
drain, as shown in Figure 6.
Setting the Sequence Delay Timer
The turn-on sequence includes two programmable delays
set by the capacitance on the TIMER pin. More precisely,
a single delay value is used at two points in the sequence.
12
PUMP
C
C
GATE
GATE
, the internal charge pump voltage. Use Equation 5
10
Q(MAX)
10
V
GATE
/
V
A t
A
GATE
•
t
U
leaves more margin for designing the
) varies with V
RAMP
U
CC
W
voltage. Consult the
U
GATE
(5)
(6)
.
In both cases, the delay provides a measure of confidence
that conditions are stable enough for the sequence to
advance.
The first TIMER delay begins once all monitor voltages
comply with their thresholds, the electronic circuit breaker
has not tripped, and V
pin sources 2 A into an external capacitor, which ramps
its voltage. A comparator trips when the TIMER pin voltage
reaches the internal 1.2V reference, then the GATE ramp
begins, and TIMER is pulled to ground. The second TIMER
delay begins after the gate of the remote sense switches is
fully ramped up. After the TIMER ramp completes, the PG
pin is activated. An internal circuit pulls-down the TIMER
pin with >100 A of current at all times, except during the
ramping periods, and when V
Calculate the nominal value for the timing capacitor by
inserting the desired delay into Equation 7:
For delay times below 60 s, be sure to limit stray capaci-
tances on the TIMER pin by using good PCB design
practices. To program essentially no delay (<1 s), float
the TIMER pin.
Internal circuitry guarantees that the TIMER pin is pulled
below 150mV (typical) before a delay cycle can begin.
Figure 6. Ramping and Damping Components on GATE Pin
C
TIMER
LTC2922
1 2 .
2
GND
V
V
V
SRC2
SRC1
SRC0
A
V
GATE
•
t
DLY
CC
is not undervoltage. The TIMER
(OPT)
(OPT)
(OPT)
0.1 F
0.1 F
0.1 F
C
C
C
D2
D1
D0
CC
is undervoltage.
R
10
R
10
R
10
2921/22 F06
Q2
C
G2
G1
G0
Q1
Q0
GATE
V
V
V
L2
L1
L0
29212fa
(7)