DS75LXS+ Maxim Integrated Products, DS75LXS+ Datasheet - Page 7

IC THERMOMETER/STAT DIG 8-SOIC

DS75LXS+

Manufacturer Part Number
DS75LXS+
Description
IC THERMOMETER/STAT DIG 8-SOIC
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS75LXS+

Function
Thermometer, Thermostat
Topology
ADC (Sigma Delta), Comparator, Register Bank
Sensor Type
Internal
Sensing Temperature
-55°C ~ 125°C
Output Type
I²C™/SMBus™
Output Alarm
No
Output Fan
No
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Temperature Threshold
Programmable
Full Temp Accuracy
+/- 2 C
Digital Output - Bus Interface
2-Wire, SMBus
Digital Output - Number Of Bits
9 bit to 12 bit
Supply Voltage (max)
3.7 V
Supply Voltage (min)
1.7 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Supply Current
1000 uA
Ic Output Type
Digital
Sensing Accuracy Range
± 2°C
Supply Voltage Range
1.7V To 3.7V
Resolution (bits)
12bit
Sensor Case Style
SOIC
No. Of Pins
8
Filter Terminals
SMD
Rohs Compliant
Yes
Temperature Sensing Range
-55°C To +125°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 3. O.S. Output Operation Example
Configuration Register
The configuration register allows the user to program various DS75LX options such as conversion resolution,
thermostat fault tolerance, thermostat polarity, thermostat operating mode, and shutdown mode. The configuration
register is arranged as shown in Figure 4 and detailed descriptions of each bit are provided in Table 2. The user
has read/write access to all bits in the configuration register except the MSb, which is a reserved read-only bit. The
entire register is volatile, and thus powers up in its default state.
Figure 4. Configuration Register
In this example the
DS75LX is configured to
have a fault tolerance of 2.
O.S. Output - Comparator Mode
O.S. Output - Interrupt Mode
MSb
0
Temperature
bit 6
R1
Inactive
Inactive
Active
bit 5
T
Active
R0
DS75LX: Digital Thermometer and Thermostat with Extended Addressing
HYST
T
OS
bit 4
F1
7 of 13
bit 3
F0
POL
bit 2
Conversions
bit 1
TM
Assumes an interrupt
has occurred
clear event
LSb
SD

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