DS18B20-SL+T&R Maxim Integrated Products, DS18B20-SL+T&R Datasheet
DS18B20-SL+T&R
Specifications of DS18B20-SL+T&R
Related parts for DS18B20-SL+T&R
DS18B20-SL+T&R Summary of contents
Page 1
... DS18B20 can derive power directly from the data line (“parasite power”), eliminating the need for an external power supply. Each DS18B20 has a unique 64-bit serial code, which allows multiple DS18B20s to function on the same 1-Wire bus. Thus simple to use one microprocessor to control many DS18B20s distributed over a large area ...
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... The control line requires a weak pullup resistor since all devices are linked to the bus via a 3-state or open-drain port (the DQ pin in the case of the DS18B20). In this bus system, the microprocessor (the master device) identifies and addresses devices on the bus using each device’s unique 64-bit code ...
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... Bus System section) after the Convert T command and the DS18B20 will respond by transmitting 0 while the temperature conversion is in progress and 1 when the conversion is done. If the DS18B20 is powered with parasite power, this notification technique cannot be used since the bus must be pulled high by a strong pullup during the entire temperature conversion ...
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... Only bits 11 through 4 of the temperature register are used in the T are 8-bit registers. If the measured temperature is lower than or equal alarm condition exists and an alarm flag is set inside the DS18B20. This flag is updated after every temperature measurement; therefore, if the alarm condition goes away, the flag will be turned off after the next temperature conversion ...
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... During the read time slot, parasite powered DS18B20s will pull the bus low, and externally powered DS18B20s will let the bus remain high. If the bus is pulled low, the master knows that it must supply the strong pullup on the 1-Wire bus during temperature conversions. ...
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... LASERED ROM CODE Each DS18B20 contains a unique 64–bit code (see Figure 6) stored in ROM. The least significant 8 bits of the ROM code contain the DS18B20’s 1-Wire family code: 28h. The next 48 bits contain a unique serial number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is calculated from the first 56 bits of the ROM code ...
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... Data is written to bytes 2, 3, and 4 of the scratchpad using the Write Scratchpad [4Eh] command; the data must be transmitted to the DS18B20 starting with the least significant bit of byte 2. To verify data integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is written ...
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... CONFIGURATION REGISTER Byte 4 of the scratchpad memory contains the configuration register, which is organized as illustrated in Figure 8. The user can set the conversion resolution of the DS18B20 using the R0 and R1 bits in this register as shown in Table 2. The power-up default of these bits and (12-bit resolution). Note that there is a direct tradeoff between resolution and conversion time. Bit 7 and bits the configuration register are reserved for internal use by the device and cannot be overwritten ...
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... BUS SYSTEM The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS18B20 is always a slave. When there is only one slave on the bus, the system is referred “single-drop” system; the system is “multidrop” if there are multiple slaves on the bus. ...
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... The presence pulse lets the bus master know that slave devices (such as the DS18B20) are on the bus and are ready to operate. Timing for the reset and presence pulses is detailed in the 1-Wire Signaling section ...
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... In parasite power mode this notification technique cannot be used since the bus is pulled high by the strong pullup during the conversion. WRITE SCRATCHPAD [4Eh] This command allows the master to write 3 bytes of data to the DS18B20’s scratchpad. The first data byte is written into the T register (byte 2 of the scratchpad), the second byte is written into the T H (byte 3), and the third byte is written into the configuration register (byte 4) ...
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... READ POWER SUPPLY [B4h] The master device issues this command followed by a read time slot to determine if any DS18B20s on the bus are using parasite power. During the read time slot, parasite powered DS18B20s will pull the bus low, and externally powered DS18B20s will let the bus remain high. See the Powering the DS18B20 section for usage information for this command ...
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... MASTER T BIT BIT 0 BIT 0 MATCH? MATCH DS18B20 T BIT DS18B20 T BIT 1 X BIT 1 MASTER T BIT BIT 1 BIT 1 MATCH? MATCH DS18B20 T BIT 63 X MASTER T DS18B20 T BIT BIT 63 MASTER T BIT BIT 63 BIT 63 MATCH? MATCH MASTER T X FUNCTION COMMAND (FIGURE 12 CCh ECh N N SKIP ROM ...
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... Figure 12. DS18B20 Function Commands Flowchart 44h MASTER T CONVERT X FUNCTION TEMPERATURE COMMAND ? Y N PARASITE POWER ? DS18B20 BEGINS CONVERSION DEVICE N CONVERTING TEMPERATURE ? Y MASTER MASTER R “0s” R “1s” B4h N READ POWER SUPPLY ? PARASITE POWERED ? MASTER MASTER R “1s” R “0s” MASTER ENABLES STRONG PULLUP ON DQ ...
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... There are two types of write time slots: “Write 1” time slots and “Write 0” time slots. The bus master uses a Write 1 time slot to write a logic 1 to the DS18B20 and a Write 0 time slot to write a logic 0 to the DS18B20. All write time slots must be a minimum of 60µs in duration with a minimum of a 1µs recovery time between individual write slots ...
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... DS18B20 will begin transmitting bus. The DS18B20 transmits leaving the bus high and transmits pulling the bus low. When transmitting a 0, the DS18B20 will release the bus by the end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output ...
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... DS18B20 is valid for 15µs after the falling edge that initiated the read time slot. Therefore, the master must release the bus and then sample the bus state within 15µs from the start of the slot. Figure 15 illustrates that the sum of T Figure 16 shows that system timing margin is maximized by keeping T and by locating the master sample time during read time slots towards the end of the 15µ ...
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... Tx 64-bit ROM code data bytes DS18B20 OPERATION EXAMPLE 2 In this example there is only one DS18B20 on the bus and it is using parasite power. The master writes to the and configuration registers in the DS18B20 scratchpad and then reads the scratchpad and H L recalculates the CRC to verify the data. The master then copies the scratchpad contents to EEPROM. ...
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... I/O 750 ±0 order to meet the PU_ACTUAL PU_IDEAL =3.0V to 5.5V) DD MAX UNITS NOTES +5 ±0.5 °C ±2 +0.8 V The lower 1000 nA 1.5 mA µA °C spec of the DS18B20, the actual . TRANSISTOR may have to be ILMAX = 5.5V. DD DS18B20 1 1,2 3 1,4 7 ...
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... Command Issued t SLOT t REC t LOW0 t LOW1 t RDV t RSTH t RSTL t PDHIGH t PDLOW C IN/OUT > 960µs, a power-on reset may occur. DS18B20 Typical Error Curve Mean Error Temperature (° 3.0V to 5.5V) DD MIN TYP MAX 2 10 50k 10 = 3.0V to 5.5V) DD MIN TYP MAX UNITS 93.75 187.5 ms ...
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... Figure 18. Timing Diagrams DS18B20 ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time © 2008 Maxim Integrated Products DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products, Inc. DS18B20 PAGES CHANGED ...