AD537KD Analog Devices Inc, AD537KD Datasheet - Page 7

• Manufacturer Part Number: AD537KD
• Description: IC V/F CONV 14-CDIP
• Manufacturer: Analog Devices Inc
• Type: Voltage to Frequencyr

Specifications of AD537KD

• Rohs Status: RoHS non-compliant
• Frequency - Max: 100kHz
• Full Scale: ±30ppm/°C
• Linearity: ±0.05%
• Mounting Type: Through Hole
• Package / Case: 14-CDIP (0.300", 7.62mm)
• Frequency: 150kHz
• Full Scale Range: 0kHz To 150kHz
• Linearity %: 0.15%
• Supply Voltage Range: 4.5V To 36V
• Digital Ic Case Style: TO-116
• No. Of Pins: 14
• Msl: MSL 1 - Unlimited
• Converter Function: VFC
• Full Scale Frequency: 150
• Power Supply Requirement: Single/Dual
• Single Supply Voltage (typ): 5/9/12/15/18/24/28V
• Single Supply Voltage (max): 36V
• Single Supply Voltage (min): 4.5V
• Dual Supply Voltage (typ): ±9/±12/±15V
• Dual Supply Voltage (min): ±5V
• Dual Supply Voltage (max): ±18V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: SBCDIP
• Lead Free Status / Rohs Status: Not Compliant

SYNCHRONOUS OPERATION
The SYNC terminal at pin 2 of the DIP package can be used to
synchronize a free running AD537 to a master oscillator, either
at a multiple or a sub-multiple of the primary frequency. The
preferred connection is shown in Figure 10. The diodes are used
to produce the proper drive magnitude from high level signals.
The SYNC terminal can also be used to shut off the oscillator.
Shorting the terminal to +V
output will go high (output NPN off).
Figure 11 shows the maximum pull-in range available at a given
signal level; the optimum signal is a 0.8 to 1.0 volt square wave;
signals below 0.1 volt will have no effect; signals above 2 volts
p-p will disable the oscillator. The AD537 can normally be syn-
chronized to a signal which forces it to a higher frequency up to
30% above the nominal free-running frequency, it can only be
brought down about 1–2%.
LINEAR PHASE LOCKED LOOP
The phase-locked-loop F/V circuit described earlier operates
from an essentially noise-free binary input. PLL’s are also used
to extract frequency information from a noisy analog signal. To
do this, the digital phase-comparator must be replaced by a lin-
ear multiplier. In the implementation shown in Figure 12, the
triangular waveform appearing across the timing capacitor is
used as one of the multiplier inputs; the signal provides the
other input. It can be shown that the mean value of the multi-
plier output is zero when the two signals are in quadrature. In
this condition, the ripple in the error signal is also quite small.
Thus, the voltage at Pin 5 is essentially zero, and the frequency
is determined primarily by the current in the timing resistor,
controlled either manually or by a control voltage.
REV. C
V
NOTE: IF V
USE THIS LIMITER
SYNC
Figure 11. Maximum Frequency Lock-ln Range vs.
Sync Signal
Figure 10. Connection for Synchronous Operation
10k
SYNC
FREQUENCY
V
>2V p-p
LOCK-IN
RANGE
SYNC
1N4148
C
1000pF
S
V
C
30%
20%
10%
IN
S
2
V
SYNC
S
0.2
2
3
4
5
6
7
1
will stop the oscillator, and the
SQUARE-WAVE INPUT VOLTS p-p
0.4
V
V
T
R
BUF
0.6
REFERENCE
PRECISION
VOLTAGE
TO-FREQ
DRIVER
0.8
CURR-
CONV
AD537
1.0
14
13
12
11
10
9
8
R
C
T
+V
f
OUT
S
–7–
Noise on the input signal affects the loop operation only slightly;
it appears as noise in the timing current, but this is averaged out
by the timing capacitor. On the other hand, if the input fre-
quency changes there is a net error voltage at Pin 5 which acts
to bring the oscillator back into quadrature. Thus, the output at
Pin 14 is a noise-free square-wave having exactly the same fre-
quency as the input signal. The effectiveness of this circuit can
be judged from Figure 13 which shows the response to an input
of 1 V rms 1 kHz sinusoid plus 1 V rms Gaussian noise. The
positive supply to the AD537 is reduced by about 4 V in order
to keep the voltages at Pins 11 and 12 within the common-mode
range of the AD534.
Since this is also a first-order loop the circuit possesses a very
wide capture range. However, even better noise-integrating
properties can be achieved by adding a filter between the multi-
plier output and the VCO input. Details of suitable filter charac-
teristics can be found in the standard texts on the subject.
Figure 13. Performance of AD537 Linear Phase Locked
Loop
By connecting the multiplier output to the lower end of the tim-
ing resistor and moving the control input to Pin 5, a high resis-
tance frequency-control input is made available. However, due
to the reduced supply voltage, this input cannot exceed +6 V.
TRANSDUCER INTERFACE
The AD537 was specifically designed to accept a broad range of
input signals, particularly small voltage signals, which may be
converted directly (unlike many V-F converters which require
signal preconditioning). The 1.00 V stable reference output is
also useful in interfacing situations, and the high input resis-
tance allows nonloading interfacing from a source of varying
resistance, such as the slider of a potentiometer.
CONTROL
0 TO –10V
INPUT
FREQ
10k
LOGIC
V
Figure 12. Linear Phase-Locked Loop
DEC/
V
GND
TEMP
SYN
REF
1
2
3
4
5
6
7
V
V
T
R
REFERENCE
BUF
PRECISION
VOLTAGE
AD537
DRIVER
CURR
CONV
FREQ
-TO-
14
13
12
11
10
9
8
V
+V
–V
OUTPUT
OS
S
S
CAP
0.01µF
±12V PK
SIGNAL
INPUT
3.9V
1V RMS SIGNAL
+1V RMS NOISE
OUTPUT
RECOVERED
FREQUENCY
SIGNAL
1
2
6
7
AD537
14
8
12
11
10
POSITE
ERROR
SIGNAL
±1V PK
–15V
+15V
COM-