LTC3723EGN-2 Linear Technology, LTC3723EGN-2 Datasheet - Page 11

• Manufacturer Part Number: LTC3723EGN-2
• Description: IC CTRLR PWM SYNC PUSHPLL 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC3723EGN-2

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 50%
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SSOP
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Supply: -

OPERATIO
very low (145µA typ) start-up current that allows the use
of 1/8W to 1/4W trickle charge start-up resistors.
The trickle charge resistor should be selected as follows:
Adding a small safety margin and choosing standard
values yields:
APPLICATION
DC/DC
Off-Line
PFC Preregulator
V
ceramic capacitor to decouple the fast transient currents
demanded by the output drivers and a bulk tantalum or
electrolytic capacitor to hold up the V
bootstrap winding, or an auxiliary regulator circuit takes
over.
Regulated bias supplies as low as 7V can be utilized to
provide bias to the LTC3723-1/LTC3723-2. Refer to
Figure 2 for various bias supply configurations.
Programming Undervoltage Lockout
The LTC3723-1/LTC3723-2 provides undervoltage lock-
out (UVLO) control for the input DC voltage feed to the
power converter in addition to the V
described in the preceding section. Input DC feed UVLO is
provided with the UVLO pin. A comparator on UVLO
compares a divided down input DC feed voltage to the 5V
precision reference. When the 5V level is exceeded on
UVLO, the SS pin is released and output switching com-
mences. At the same time a 10µA current is enabled which
flows out of UVLO into the voltage divider connected to
CC
R
C
(minimum UVLO hysteresis)
HOLDUP
START(MAX)
should be bypassed with a 0.1µF to 1µF multilayer
12V ±10%
V
CC
1.5k
= (I
CC
= V
Figure 2. Bias Configurations
U
1N5226
3V
+ I
1µF
IN(MIN)
DRIVE
85V to 270V
V
36V to 72V
) • t
– 10.7V/250µA
V
IN
390V
BIAS
RANGE
V
DELAY
< V
CC
DC
1N914
UVLO
RMS
V
/3.8V
IN
CC
R
CC
START
1µF
supply before the
UVLO function
+
R
372312 F02
100k
430k
1.4M
C
START
HOLD
UVLO. The amount of DC feed hysteresis provided by this
current is: 10µA • R
threshold is: 5V • {(R
voltage applied to UVLO is present and greater than 5V
prior to the V
UVLO logic will prevent output switching until the follow-
ing three conditions are met: (1) V
V
UVLO can also be used to enable and disable the power
converter. An open drain transistor connected to UVLO as
shown in Figure 3 provides this capability.
Off-Line Bias Supply Generation
If a regulated bias supply is not available to provide V
voltage to the LTC3723-1/LTC3723-2 and supporting
circuitry, one must be generated. Since the power require-
ment is small, approximately 1W, and the regulation is not
critical, a simple open-loop method is usually the easiest
and lowest cost approach. One method that works well is
to add a winding to the main power transformer, and post
regulate the resultant square wave with an L-C filter (see
Figure 4a). The advantage of this approach is that it
maintains decent regulation as the supply voltage varies,
and it does not require full safety isolation from the input
winding of the transformer. Some manufacturers include
a primary winding for this purpose in their standard
REF
is in regulation and (3) UVLO pin is greater than 5V.
Figure 4a. Auxiliary Winding Bias Supply
LTC3723-1/LTC3723-2
CC
ON OFF
UVLO circuitry activation, then the internal
Figure 3. System UVLO Setup
15V*
*OPTIONAL
TOP
TOP
, (Figure 3). The system UVLO
R
START
+ R
+
R
V
R
IN
TOP
BOTTOM
BOTTOM
C
CC
HOLD
UVLO is enabled, (2)
2k
)/R
372312 F03
UVLO
372312 F04a
BOTTOM
V
CC
1µF
}. If the
11
372312f
CC