DS1050Z-001+ Maxim Integrated Products, DS1050Z-001+ Datasheet - Page 9

• Manufacturer Part Number: DS1050Z-001+
• Description: IC PWM 5BIT 1KHZ 2-WIRE 8SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS1050Z-001+

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 1kHz
• Duty Cycle: 100%
• Voltage - Supply: 2.7 V ~ 5.5 V
• Buck: No
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 1kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. C
11. A PWM output duty cycle change will occur with 2 periods of the output frequency when a change is
12. The absolute frequency output of the PWM can be expected to fall within a ±20% range from the
13. The DS1050 is a 5-bit PWM. The output duty cycles of the device range from 0% to 100% in step
14. Absolute Linearity is used to compare measured duty cycle against expected duty cycle as
15. Relative Linearity is used to determine the change in duty cycle between adjacent or successive duty
All voltages are referenced to ground.
I
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
Address Inputs, A0, A1, and A2, should be tied to either V
address selections.
I
logic levels.
A fast mode device can be used in a standard mode system, but the requirement
t
the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line t
line is released.
After this period, the first clock pulse is generated.
The maximum t
SCL signal.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
V
initiated.
nominal specified value of the device.
sizes of 3.125%. The “Set PWM Duty Cycle 100%” allows the PWM output to be set to full-on.
determined by the DAC setting. The DS1050 is specified to provide an absolute linearity of ±0.5
LSB.
cycle settings. The DS1050 is specified to provide a relative linearity specification of ±0.25 LSB.
SU:DAT
CC
STBY
B
IH MIN
– total capacitance of one bus line in picofarads, timing referenced to (0.9)(V
specified with outputs open.
specified for V
> 250ns must then be met. This will automatically be the case if the device does not stretch
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
SU:DAT
CC
has only to be met if the device does not stretch the LOW period (t
between 3.0V and 5.0V, control port logic pins are driven to the appropriate
9 of 17
RMAX
+ t
SU:DAT
CC
or GND depending on the desired
= 1000 + 250=1250ns before the SCL
CC
is switched off.
CC
) and (0.1)(V
LOW
) of the
CC
).