MAX1980ETP+T Maxim Integrated Products, MAX1980ETP+T Datasheet - Page 25

• Manufacturer Part Number: MAX1980ETP+T
• Description: IC CNTRLR QUICK-PWM 20-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX1980ETP+T

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 550kHz
• Duty Cycle: 50%
• Voltage - Supply: 4 V ~ 28 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 20-TQFN Exposed Pad
• Frequency-max: 550kHz
• Input Voltage: 4 V to 28 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The current-balance compensation capacitor (C
integrates the difference of the master and slave cur-
rent-sense signals, while the compensation resistor
improves transient response by increasing the phase
margin. This allows the user to optimize the dynamics
of the current-balance loop. Excessively large capaci-
tor values increase the integration time constant, result-
ing in larger current differences between the phases
during transients. Excessively small capacitor values
allow the current loop to respond cycle-by-cycle but
can result in small DC current variations between the
phases. Likewise, excessively large series resistance
can also cause DC current variations between the
phases. Small series resistance reduces the phase
margin, resulting in marginal stability in the current-bal-
ance loop. For most applications, a 470pF capacitor
and 10kΩ series resistor from COMP to the converter’s
output voltage works well.
The compensation network can be tied to V
include the feed-forward term due to the master’s on
time. (See the On-Time Control and Active Current
Balancing section.) To reduce noise pick-up in applica-
tions that have a widely distributed layout, it is some-
times helpful to connect the compensation network to
quiet analog ground rather than V
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the
processors power dissipation. When the output is
loaded, an external operational amplifier (Figure 7)
increases the signal fed back to the master’s feedback
input. The additional gain provided by the op amp
allows the use of low-value current-sense resistors, sig-
nificantly reducing the power dissipated in the current-
sense resistors when connecting the feedback voltage
directly to the current sense resistor. The load transient
response of this control loop is extremely fast yet well
controlled, so the amount of voltage change can be
accurately confined within the limits stipulated in the
microprocessor power supply guidelines. To under-
stand the benefits of dynamically adjusting the output
voltage, see the Voltage Positioning and Effective
Efficiency section.
The voltage positioned circuit determines the load current
from the voltage across the current-sense resistors
(R
and output capacitors, as shown in Figure 7. The voltage
drop may be determined by the following equation:
SENSE
Driver Disable for Multiphase DC-DC Converter
Current-Balance Compensation (COMP)
= R
CM
= R
______________________________________________________________________________________
CS
Setting Voltage Positioning
) connected between the inductors
OUT
Quick-PWM Slave Controller with
.
OUT
COMP
to
)
where η is the number of phases summed together.
When the slave controller is disabled, the current-sense
summation maintains the proper voltage positioned
slope. Select the positive input summing resistors (R
R
Powering new mobile processors requires careful
attention to detail to reduce cost, size, and power dissi-
pation. As CPUs became more power hungry, it was
recognized that even the fastest DC-DC converters
were inadequate to handle the transient power require-
ments. After a load transient, the output instantly
changes by ESR
converters respond by regulating the output voltage
back to its nominal state after the load transient occurs
(Figure 8). However, the CPU only requires that the out-
put voltage remain above a specified minimum value.
Dynamically positioning the output voltage to this lower
Figure 7. Voltage Positioning Gain
(MASTER)
D
) using the following equation:
FB
C
FB
V
V
R
VPS
VPS
FB
Applications Information
=
=
COUT






R
1
1
η
+
A
MAX4322
+
=
η
R
✕
R
R
R
R
B
Voltage Positioning and
MASTER
SLAVE
C
B
B
C
∆I
RC
SUPPLY
5V BIAS



|| η



LOAD
I
LOAD SENSE
(



I
LOAD
Effective Efficiency
R
L
L
C
M
S
η
R
D
. Conventional DC-DC
R
)
= R
R
A
A



R
R
SENSE
CS
R
R
CM
E
= R
= R
R
CM
B
B
BOARD
RESISTANCE
A
25
=