CS5171EDR8G ON Semiconductor, CS5171EDR8G Datasheet - Page 12

• Manufacturer Part Number: CS5171EDR8G
• Description: IC MULTI CONFIG SYNC 1.5A 8SOIC
• Manufacturer: ON Semiconductor
• Type: Step-Up (Boost), Flyback, Forward Converter, Sepicr

Specifications of CS5171EDR8G

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Current - Output: 1.5A
• Frequency - Switching: 280kHz
• Voltage - Input: 2.7 ~ 30 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Mounting Style: SMD/SMT
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: CS5171EDR8GOSTR

The first zero generated by C1 and R1 is:
has at least a 45° phase margin at the crossover frequency.
Therefore, this zero should be placed close to the pole
generated in the power stage which can be identified at
frequency:
where:
filter’s ESR zero or at half the switching frequency. Placing
the pole at this frequency will cut down on switching noise.
The frequency of this pole is determined by the value of C2
and R1:
design the frequency response with a −20 dB per decade
slope, until unity−gain crossover. The crossover frequency
should be selected at the midpoint between f
the phase margin is maximized.
Negative Voltage Feedback
impedance as shown in Figure 33, its induced error has to be
considered. If a voltage divider is used to scale down the
negative output voltage for the NFB pin, the equation for
calculating output voltage is:
f Z1 +
f P +
f P2 +
Figure 32. Bode Plot of the Compensation Network
The phase lead provided by this zero ensures that the loop
C
R
The high frequency pole, f
One simple method to ensure adequate phase margin is to
Since the negative error amplifier has finite input
O
LOAD
2pC O R LOAD
= equivalent output capacitance of the error amplifier
≈120pF;
2pC1R1
2pC2R1
*V OUT +
= load resistance.
1
1
1
f
P1
Shown in Figure 31
Frequency (LOG)
*2.5 (R1 ) R2)
f
Z1
R2
P2
, can be placed at the output
f
P2
*10 mA
Z1
and f
P2
R1
http://onsemi.com
where
12
the design target will be less than 0.1 V. If the tolerances of
the negative voltage reference and NFB pin input current are
considered, the possible offset of the output V
in the range of:
V
the maximum output voltage plus the output diode forward
voltage. The diode forward voltage is typically 0.5 V for
Schottky diodes and 0.8 V for ultrafast recovery diodes
where:
where:
spike superimposed on top of the steady−state voltage.
Usually this voltage spike is caused by transformer leakage
inductance charging stray capacitance between the V
PGND pins. To prevent the voltage at the V
exceeding the maximum rating, a transient voltage
suppressor in series with a diode is paralleled with the
primary windings. Another method of clamping switch
voltage is to connect a transient voltage suppressor between
the V
*0.0.5 (R1 ) R2)
SW
It is shown that if R1 is less than 10 k, the deviation from
In the boost topology, V
V
In the flyback topology, peak V
N = transformer turns ratio, primary over secondary.
When the power switch turns off, there exists a voltage
F
Figure 33. Negative Error Amplifier and NFB Pin
Voltage Limit
SW
= output diode forward voltage.
V SW(MAX) + V CC(MAX) )(V OUT )V F )
−V
pin and ground.
R2
OUT
R1
R2
V SW(MAX) + V OUT(MAX) )V F
NFB
v
* (15 mA
250 kW
R
SW
0.0.5 (R1 ) R2)
IN
pin maximum voltage is set by
2 V
R2
SW
200 kW
R
Negative Error−Amp
R1) v V OFFSET
P
−
+
voltage is governed by:
* (5 mA
OFFSET
SW
pin from
N
SW
varies
and
R1)