ADP1829ACPZ-R7 Analog Devices Inc, ADP1829ACPZ-R7 Datasheet
ADP1829ACPZ-R7
Specifications of ADP1829ACPZ-R7
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ADP1829ACPZ-R7 Summary of contents
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FEATURES Fixed frequency operation: 300 kHz, 600 kHz, or synchronized operation MHz Supply input range: 3 Wide power stage input range Interleaved operation results in smaller, low cost ...
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ADP1829 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Typical Application Circuit ............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Functional Block Diagram .............................................................. 6 ...
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SPECIFICATIONS ENx = FREQ = PV = VREG = 5 V, SYNC = GND, T extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at T Table 1. Parameter POWER SUPPLY ...
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ADP1829 Parameter OSCILLATOR Oscillator Frequency 2 SYNC Synchronization Range SYNC Minimum Input Pulse Width CURRENT SENSE CSL1, CSL2 Threshold Voltage CSL1, CSL2 Output Current Current Sense Blanking Period GATE DRIVERS DH1, DH2 Rise Time DH1, DH2 Fall Time DL1, DL2 ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating IN, EN1, EN2 −0 +20.5 V BST1, BST2 −0 +30 V BST1, BST2 to SW1, SW2 −0 CSL1, CSL2 − +30 V SW1, ...
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ADP1829 FUNCTIONAL BLOCK DIAGRAM VREG 0.6V REF 0.8V LDOSD EN1 EN2 FREQ OSCILLATOR PHASE 1 = 0° PHASE 2 = 180° SYNC COMP1 FB1 TRK1 0.6V SS1 COMP2 FB2 TRK2 0.6V UV2 SS2 GND IN LINEAR REG 0.75V 0.55V THERMAL ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 FB1 Feedback Voltage Input for Channel 1. Connect a resistor divider from the buck regulator output to GND and tie the tap to FB1 to ...
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ADP1829 Pin No. Mnemonic Description 23 BST1 Boost Capacitor Input for Channel 1. Powers the high-side gate driver DH1. Connect a 0.22 μF to 0.47 μF ceramic capacitor from BST1 to SW1 and a Schottky diode from PV to BST1. ...
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TYPICAL PERFORMANCE CHARACTERISTICS 12V 20V 15V LOAD CURRENT (A) Figure 4. Efficiency vs. Load Current 1.8 ...
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ADP1829 4.960 4.956 4.952 4.948 4.944 4.940 LOAD CURRENT (mA) Figure 10. VREG vs. Load Current 100 150 LOAD CURRENT (mA) Figure 11. VREG Current-Limit Foldback T ...
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AC-COUPLED, OUT1 100mV/DIV LOAD ON LOAD OFF LOAD OFF 100µs/DIV Figure 16. 1 Load Transient Response SS1, 0.5V/DIV V , 0.5V/DIV OUT1 INPUT CURRENT, 0.2A/DIV SHORT CIRCUIT APPLIED 4ms/DIV SHORT CIRCUIT ...
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ADP1829 T SOFT START, 1V/DIV 4ms/DIV Figure 22. Power-On Response, EN Tied to IN TRACK PIN VOLTAGE, T 200mV/DIV FEEDBACK PIN VOLTAGE, 200mV/DIV 20ms/DIV Figure 23. Output Voltage Tracking Response V , 5V/DIV IN EN2 PIN, 5V/DIV V , 2V/DIV ...
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THEORY OF OPERATION The ADP1829 is a dual, synchronous, PWM buck controller capable of generating output voltages down to 0.6 V and output currents in the tens of amps. The switching of the regulators is interleaved for reduced current ripple. ...
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ADP1829 If FREQ is driven low, the recommended SYNC input frequency is between 600 kHz and 1.2 MHz. If FREQ is driven high, the recommended SYNC frequency is between 1.2 MHz and 2 MHz. The FREQ setting should be carefully ...
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MOSFET DRIVERS The DH1 and DH2 pins drive the high-side switch MOSFETs. These are boosted 5 V gate drivers that are powered by bootstrap capacitor circuits. This configuration allows the high- side, N-channel MOSFET gate to be driven above the ...
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ADP1829 APPLICATIONS INFORMATION SELECTING THE INPUT CAPACITOR The input current to a buck converter is a pulse waveform zero when the high-side switch is off and approximately equal to the load current when it is on. The input ...
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In the case of output capacitors where the impedance of the ESR and ESL are small at the switching frequency, for instance, where the output capacitor is a bank of parallel MLCC capacitors, the capacitive impedance dominates and the ripple ...
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ADP1829 SETTING THE CURRENT LIMIT The current-limit comparator measures the voltage across the low-side MOSFET to determine the load current. The current limit is set through the current-limit resistor, R The current sense pins, CSL1 and CSL2, source 50 μA ...
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COMPENSATING THE VOLTAGE MODE BUCK REGULATOR Assuming the LC filter design is complete, the feedback control system can then be compensated. Good compensation is critical to proper operation of the regulator. Calculate the quantities in Equation 19 through Equation 47 ...
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ADP1829 The rest of the system gain is needed to reach crossover. The total gain of the system, therefore, is given MOD FILTER COMP where the ...
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Type II Compensator G (dB PHASE Z P –180° –270° TOP FROM V OUT EA R BOT COMP VREF Figure 28. Type II Compensation If the output capacitor ESR zero frequency ...
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ADP1829 Because of the finite output current drive of the error amplifier, C needs to be less than 10 nF larger than 10 nF, choose a I larger R and recalculate R and C until C TOP ...
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COINCIDENT TRACKING The most common application is coincident tracking, used in core vs. I/O voltage sequencing and similar applications. Coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. Connect the ...
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ADP1829 Setting the Channel 2 Undervoltage Threshold for Ratiometric Tracking If FB2 is regulated to a voltage lower than 0 configuring TRK2 for ratiometric tracking, the Channel 2 undervoltage threshold can be set appropriately by splitting the top ...
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PCB LAYOUT GUIDELINES In any switching converter, some circuit paths carry high dI/dt, which can create spikes and noise. Other circuit paths are sensitive to noise. Still others carry high dc current and can produce significant IR voltage drops. The ...
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ADP1829 LFCSP PACKAGE CONSIDERATIONS The LFCSP package has an exposed die paddle on the bottom that efficiently conducts heat to the PCB. To achieve the optimum performance from the LFCSP package, give special consideration to the layout of the PCB. ...
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APPLICATION CIRCUITS The ADP1829 controller can be configured to regulate outputs with loads of more than the power components, such as the inductor, MOSFETs and the bulk capacitors, are chosen carefully to meet the power requirement. The ...
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ADP1829 The ADP1829 can also be configured to drive an output load of less than 1 A. Figure 35 shows a typical application circuit that drives 1.5 A and 3 A loads in all multilayer ceramic capacitor (MLCC) solutions. Note ...
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... SEATING PLANE ORDERING GUIDE 1, 2 Model Temperature Range ADP1829ACPZ-R7 −40°C to +85°C ADP1829-EVALZ ADP1829-BL1-EVZ ADP1829-BL2-EVZ RoHS Compliant Part. 2 For the ADP1829-BL1-EVZ and the ADP1829-BL2-EVZ, users can generate schematic design and build of materials from the Analog Devices, Inc., ADIsimPower™ at www ...
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ADP1829 NOTES Rev Page ...
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NOTES Rev Page ADP1829 ...
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ADP1829 NOTES ©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06784-0-1/11(B) Rev Page ...